OpenASIP

OpenASIP (formerly TTA-based Co-design Environment or TCE) is an open application-specific instruction-set toolset. It can be used to design and program customized processors based on the energy efficient Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.

OpenASIP development is led by the Customized Parallel Computing (CPC) group at the Tampere University, Finland. Further reading: LLVM project blog post about OpenASIP.

Discussion channels

You can subscribe to a mailing list for OpenASIP-related discussions here.

News and updates

November 23rd, 2022: OpenASIP 2.0 released!

The first OpenASIP version with preliminary RISC-V customization support is now out!

July 23rd, 2018: A tutorial slide deck with clickable videos uploaded

The slide set (39M) contains clickable videos and goes through most of the tool set. It was first presented in OpenSuco 3 workshop organized within the ISC High Performance 2018 conference (June 28th in Frankfurt, Germany).

October 4th, 2017: OpenASIP-based demo featured on the lab's blog

A demonstration featuring a neural network coprocessor designed with OpenASIP was shown at CIVIT.

For more info, read the post on the Pervasive Computing blog.

Feature highlights

  • Compiler:
    • LLVM based, Clang as the default frontend
    • OpenCL support via the pocl project
    • Basic block instruction scheduler (top-down and bottom-up)
    • Delay slot filling
    • Software bypassing
    • (experimental) Operand sharing
    • Custom operation support
    • Parallel TTA assembler
    • Software and hardware floating point support
    • Basic debugging info support
    • Multiple address space support
    • Support for native computation on half precision floats (fp16)
  • Simulator:
    • Graphical and command line user interfaces
    • Interpretive debugging engine for cycle stepping
    • Static compiled engine for fast simulation with basic block granularity (but cycle count accuracy)
    • Dynamic compiled engine for improved startup time with fast simulation
    • SystemC integration API
  • Processor and Program Image Generation:
    • Support for generating implementation for the designed processor as VHDL. Experimental support for Verilog.
    • Generates bit image of the program (supported formats include the Altera MIF)
    • Dictionary-based instruction compression
    • Automated generation of the files needed to integrate the core to different FPGA platforms.
    • IP-XACT 1.5 support
  • Design space exploration:
    • Automated, manual and semi-automatic algorithm implementations
    • Tools that allow easy modification of the target architecture
    • Automated search of the connectivity design space
  • Integrated Development Environment tools:
    • Graphical user interface (GUI) for editing architecture resources
    • GUI for editing operation set definitions