OpenASIP (formerly TTA-based Co-design Environment or TCE) is an open application-specific instruction-set toolset. It can be used to design and program customized processors based on the energy efficient Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
In a recent work Yanık et al. used OpenASIP toolset as a basis for rapidly extending the instruction set of RISC-V cores. They use Vitis HLS tool to generate custom function units (FU) directly from C program descriptions. What a great idea! The user needs to only give the description of the custom operation in C and the tools generate a full function unit out of it. After that, their scripts integrate the function unit into a RISC-V ASIP using OpenASIP. It’s great to see how our easy-to-use custom FU integration enables people to create experiments like this. Their paper DELTA-V: An Open-Source High-Level Synthesis Driven ASIP Design Automation Tool for RISC-V Microprocessors was published in 2023 14th International Conference on Electrical and Electronics Engineering (ELECO). The paper is available here and the source code here.
Interesting audio processor case study designed with OpenaASIP was published by University of Turin researchers who received good results even while using a fully connected interconnection matrix: The power consumption of the developed TTA architecture was found to be significantly lower compared to traditional software-based approaches, with a total estimated power of approximately 350 mW. Details can be found in the publication and the master's thesis.
The first OpenASIP version with preliminary RISC-V customization support is now out!
The slide set (39M) contains clickable videos and goes through most of the tool set. It was first presented in OpenSuco 3 workshop organized within the ISC High Performance 2018 conference (June 28th in Frankfurt, Germany).
A demonstration featuring a neural network coprocessor designed with OpenASIP was shown at CIVIT.
For more info, read the post on the Pervasive Computing blog.