TTA-based Co-Design Environment (TCE) is an open application-specific instruction-set toolset. It can be used to design and program customized processors based on the energy efficient Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
TCE development is led by the Customized Parallel Computing (CPC) group at the Department of Pervasive Computing of Tampere University, Finland. Further reading: LLVM project blog post about TCE.
News and updates
April 12th, 2019: TCE 1.19 released
A new version of the toolset is now available for download.
See the release announcement and the change summary for details. Install instructions.
September 21st, 2018: TCE 1.18 released
A new version of the toolset is now available for download.
See the release announcement and the change summary for details. Install instructions.
July 23rd, 2018: A tutorial slide deck with clickable videos uploaded
The slide set (39M) contains clickable videos and goes through most of the tool set. It was first presented in OpenSuco 3 workshop organized within the ISC High Performance 2018 conference (June 28th in Frankfurt, Germany).
March 12th, 2018: TCE 1.17 released
A new version of the toolset is now available for download.
See the release announcement and the change summary for details. Install instructions.
October 4th, 2017: TCE-based demo featured on the lab's blog
A demonstration featuring a neural network coprocessor designed with TCE was shown at CIVIT.
For more info, read the post on the Pervasive Computing blog.
September 20th, 2017: TCE 1.16 released
A new version of the toolset is now available for download.
See the release announcement and the change summary for details. Install instructions.
May 17th, 2017: New publications added
- Jukka Teittinen, Markus Hiienkari, Indrė Žliobaitėb, Jaakko Hollmen, Heikki Berg, Juha Heiskala, Timo Viitanen, Jesse Simonsson, Lauri Koskinen:
"A 5.3 pJ/op approximate TTA VLIW tailored for machine learning",
in Microelectronics Journal, Volume 61, March 2017 (download). - Pekka Jääskeläinen, Timo Viitanen, Jarmo Takala, Heikki Berg:
"HW/SW Co-design Toolset for Customization of Exposed Datapath Processors",
in Computing Platforms for Software-Defined Radio (book chapter pp 147-164), December 2016 (download). - Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
"Xor-Masking: a Low-Overhead Method for Instruction Fetch Energy Reduction with Emerging SRAM Technologies",
in SiPS 2016: IEEE Workshop on Signal Processing Systems (Dallas, Texas, October 2016) (download). - Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Karen Egiazarian, Aram Danielyan, Cristóvão Cruz:
"OpenCL Programmable Exposed Datapath High Performance Low-Power Computational Imaging Accelerator",
in IEEE Nordic Circuits and Systems Conference (Copenhagen, Denmark, November 2016) (download). - Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
"Aggressively Bypassing List Scheduler for Transport Triggered architectures",
in SAMOS XVI: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2016) (download). - N.Behmann, C. Seifert, G. Paya-Vaya, H. Blume, P. Jääskeläinen, J.Multanen, H. Kultala, J. Takala, J. Thiemann, S. van de Par:
"Customized High Performance Low Power Processor for Binaural Speaker Localization",
in IEEE Int'l Conference on Electronics, Circuits, & Systems (Monte Carlo, Monaco, December 2016) (download).
Feature highlights
- Compiler:
- LLVM based, Clang as the default frontend
- OpenCL support via the pocl project
- Basic block instruction scheduler (top-down and bottom-up)
- Delay slot filling
- Software bypassing
- (experimental) Operand sharing
- Custom operation support
- Parallel TTA assembler
- Software and hardware floating point support
- Basic debugging info support
- Multiple address space support
- Support for native computation on half precision floats (fp16)
- Simulator:
- Graphical and command line user interfaces
- Interpretive debugging engine for cycle stepping
- Static compiled engine for fast simulation with basic block granularity (but cycle count accuracy)
- Dynamic compiled engine for improved startup time with fast simulation
- SystemC integration API
- Processor and Program Image Generation:
- Support for generating implementation for the designed processor as VHDL. Experimental support for Verilog.
- Generates bit image of the program (supported formats include the Altera MIF)
- Dictionary-based instruction compression
- Automated generation of the files needed to integrate the core to different FPGA platforms.
- IP-XACT 1.5 support
- Design space exploration:
- Automated, manual and semi-automatic algorithm implementations
- Tools that allow easy modification of the target architecture
- Automated search of the connectivity design space
- Integrated Development Environment tools:
- Graphical user interface (GUI) for editing architecture resources
- GUI for editing operation set definitions