| addICToNetlist(const ProGe::NetlistGenerator &generator, ProGe::NetlistBlock &netlistBlock) | DefaultICGenerator | |
| altSignalMap_ | DefaultICGenerator | private |
| busAltSignal(const TTAMachine::Bus &bus, const TTAMachine::Socket &socket) | DefaultICGenerator | private |
| BusAltSignalMap typedef | DefaultICGenerator | private |
| busCntrlPortMap_ | CentralizedControlICGenerator | private |
| busCntrlPortOfSocket(const std::string &socketName) const | CentralizedControlICGenerator | |
| busConnections | DefaultICGenerator | private |
| busControlWidth(TTAMachine::Socket::Direction direction, int busConns) | DefaultICGenerator | privatestatic |
| busMuxControlPort(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| busMuxDataPort(const TTAMachine::Bus &bus, int index) | DefaultICGenerator | privatestatic |
| busMuxEnablePort(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| busMuxEntityName(TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| busSignal(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| BusSocketMap typedef | DefaultICGenerator | |
| busTraceStartingCycle_ | DefaultICGenerator | private |
| busWidthGeneric(int bus) | DefaultICGenerator | privatestatic |
| CentralizedControlICGenerator() | CentralizedControlICGenerator | |
| convertDirection(TTAMachine::Socket::Direction direction) | DefaultICGenerator | privatestatic |
| createSignalsForIC(std::ostream &stream) | DefaultICGenerator | private |
| dataCntrlPortMap_ | CentralizedControlICGenerator | private |
| dataCntrlPortOfSocket(const std::string &socketName) const | CentralizedControlICGenerator | |
| dataControlWidth(TTAMachine::Socket::Direction direction, int portConns) | DefaultICGenerator | privatestatic |
| dataWidthGeneric(int port) | DefaultICGenerator | privatestatic |
| declareSocketEntities(std::ostream &stream) const | DefaultICGenerator | private |
| DefaultICGenerator(const TTAMachine::Machine &machine) | DefaultICGenerator | |
| entityNameStr_ | DefaultICGenerator | private |
| exportBustrace_ | DefaultICGenerator | private |
| generateBusTrace_ | DefaultICGenerator | private |
| generatedInputSockets_ | DefaultICGenerator | private |
| generatedOutputSockets_ | DefaultICGenerator | private |
| generateInputMux(int segmentConns, std::ofstream &stream) const | DefaultICGenerator | private |
| generateInputSocketRuleForBus(int bus, int ind, std::ofstream &stream) const | DefaultICGenerator | private |
| generateInterconnectionNetwork(const std::string &dstDirectory) | DefaultICGenerator | |
| generateOutputSocket(int portConns, int segmentConns, std::ofstream &stream) const | DefaultICGenerator | private |
| generateSocket(TTAMachine::Socket::Direction direction, int portConns, int segmentConns, const std::string &dstDirectory) const | DefaultICGenerator | private |
| generateSocketsAndMuxes(const std::string &dstDirectory) | DefaultICGenerator | private |
| getBusConnections() const | DefaultICGenerator | virtual |
| glockPort() const | CentralizedControlICGenerator | |
| glockPort_ | CentralizedControlICGenerator | private |
| hasGlockPort() const | CentralizedControlICGenerator | |
| icBlock_ | DefaultICGenerator | private |
| indentation(unsigned int level) | DefaultICGenerator | privatestatic |
| inputMuxEntityName(int conns) const | DefaultICGenerator | private |
| inputSocketBusPort(int bus) | DefaultICGenerator | privatestatic |
| inputSocketControlValue(const TTAMachine::Socket &socket, const TTAMachine::Segment &segment) const | DefaultICGenerator | virtual |
| inputSocketDataPort(const std::string &socket) | DefaultICGenerator | privatestatic |
| inputSocketDataPortWidth(const TTAMachine::Socket &socket) | DefaultICGenerator | privatestatic |
| inputSockets(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| isBusConnected(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| isBustraceEnabled() | DefaultICGenerator | |
| isGcuPort(const TTAMachine::Port *port) const | DefaultICGenerator | private |
| language_ | DefaultICGenerator | private |
| machine_ | DefaultICGenerator | private |
| mapBusCntrlPortOfSocket(const std::string &socketName, ProGe::NetlistPort &port) | CentralizedControlICGenerator | protected |
| mapDataCntrlPortOfSocket(const std::string &socketName, ProGe::NetlistPort &port) | CentralizedControlICGenerator | protected |
| mapSImmCntrlPort(const std::string &busName, ProGe::NetlistPort &port) | CentralizedControlICGenerator | protected |
| mapSImmDataPort(const std::string &busName, ProGe::NetlistPort &port) | CentralizedControlICGenerator | protected |
| maxOutputSocketDataPortWidth(const TTAMachine::Socket &socket) | DefaultICGenerator | privatestatic |
| NetlistPortMap typedef | CentralizedControlICGenerator | private |
| outputSocketBusPort(int bus) | DefaultICGenerator | privatestatic |
| outputSocketCntrlPinForSegment(const TTAMachine::Socket &socket, const TTAMachine::Segment &segment) const | DefaultICGenerator | virtual |
| outputSocketDataControlValue(const TTAMachine::Socket &socket, const TTAMachine::Port &port) const | DefaultICGenerator | virtual |
| outputSocketDataPort(const std::string &socket, int port) | DefaultICGenerator | privatestatic |
| outputSocketDataPort(int port) | DefaultICGenerator | privatestatic |
| outputSocketDataPortWidth(const TTAMachine::Socket &socket, int port) | DefaultICGenerator | privatestatic |
| outputSocketEntityName(int busConns, int portConns) const | DefaultICGenerator | private |
| outputSockets(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| setBusTraceStartingCycle(unsigned int cycle) | DefaultICGenerator | |
| setExportBustrace(bool export_bt) | DefaultICGenerator | |
| setFPGAOptimization(bool optimized) | DefaultICGenerator | |
| setGenerateBusTrace(bool generate) | DefaultICGenerator | |
| setGlockPort(ProGe::NetlistPort &glockPort) | CentralizedControlICGenerator | protected |
| SetHDL(ProGe::HDL language) | DefaultICGenerator | |
| simmCntrlPort(const std::string &busName) const | CentralizedControlICGenerator | |
| simmCntrlPortMap_ | CentralizedControlICGenerator | private |
| simmControlPort(const std::string &busName) | DefaultICGenerator | privatestatic |
| simmDataPort(const std::string &busName) | DefaultICGenerator | privatestatic |
| CentralizedControlICGenerator::simmDataPort(const std::string &busName) const | CentralizedControlICGenerator | |
| simmDataPortMap_ | CentralizedControlICGenerator | private |
| simmPortWidth(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| simmSignal(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| simmSocket(const TTAMachine::Bus &bus) | DefaultICGenerator | privatestatic |
| socketBusControlPort(const std::string &name) | DefaultICGenerator | privatestatic |
| socketDataControlPort(const std::string &name) | DefaultICGenerator | privatestatic |
| socketDataPortMap_ | CentralizedControlICGenerator | private |
| socketEntityName(TTAMachine::Socket &socket) const | DefaultICGenerator | private |
| socketFileName(const ProGe::HDL language, TTAMachine::Socket::Direction direction, int portConns, int segmentConns) | DefaultICGenerator | privatestatic |
| socketIsGenerated(const TTAMachine::Socket &socket) | DefaultICGenerator | private |
| socketIsGenerated(int segmentConns, int portConns, TTAMachine::Socket::Direction direction) | DefaultICGenerator | private |
| SocketSignalMap typedef | DefaultICGenerator | private |
| verifyCompatibility() const | DefaultICGenerator | |
| writeBusDumpCode(std::ostream &stream) const | DefaultICGenerator | private |
| writeBustraceExportCode(std::ostream &stream) const | DefaultICGenerator | private |
| writeInputSocketComponentDeclaration(const ProGe::HDL language, int segmentConns, int ind, std::ostream &stream) | DefaultICGenerator | privatestatic |
| writeInterconnectionNetwork(std::ostream &stream) | DefaultICGenerator | private |
| writeOutputSocketComponentDeclaration(const ProGe::HDL language, int portConns, int segmentConns, int ind, std::ostream &stream) | DefaultICGenerator | privatestatic |
| ~CentralizedControlICGenerator() | CentralizedControlICGenerator | virtual |
| ~DefaultICGenerator() | DefaultICGenerator | virtual |
