OpenASIP
2.0
|
This is the complete list of members for FUGen, including all inherited members.
addRegisterIfMissing(std::string name, int width, HDLGenerator::WireType wt=HDLGenerator::WireType::Auto) | FUGen | private |
addressWidth_ | FUGen | private |
adfFU_ | FUGen | private |
backRegistered_ | FUGen | private |
baseOperations_ | FUGen | private |
behaviour_ | FUGen | private |
buildOperations() | FUGen | private |
buildReplaces(std::string opName) | FUGen | private |
checkForValidity() | FUGen | private |
constantName(ConstantNode *node, OperationDAG *dag) | FUGen | private |
constantName(DAGConstant dag) | FUGen | private |
copyImplementation(std::string file, std::string format, bool isSynthesizable) | FUGen | private |
core_ | FUGen | private |
createExternalInterfaces(bool genIntegrator) | FUGen | private |
createFUHeaderComment() | FUGen | private |
createImplementationFiles() | FUGen | private |
createMandatoryPorts() | FUGen | private |
createOperationResources() | FUGen | private |
createOutputPipeline() | FUGen | private |
createPortPipeline() | FUGen | private |
createShadowRegisters() | FUGen | private |
dagConstantCount_ | FUGen | private |
dagConstants_ | FUGen | private |
DAGNodeOperandWidth(OperationDAGNode &node, int id, OperationDAG *dag) | FUGen | private |
extIfaces_ | FUGen | private |
extInputs_ | FUGen | private |
extOutputs_ | FUGen | private |
finalizeHDL() | FUGen | private |
findAbsolutePath(std::string file) | FUGen | private |
frontRegistered_ | FUGen | private |
fu_ | FUGen | private |
fug_ | FUGen | private |
FUGen()=delete | FUGen | |
FUGen(const FUGen &)=delete | FUGen | |
FUGen(const ProGeOptions &options, std::vector< std::string > globalOptions, IDF::FUGenerated &fug, const TTAMachine::Machine &machine, ProGe::NetlistBlock *core) | FUGen | inline |
globalOptions_ | FUGen | private |
hasToken(std::string line, std::string token) | FUGen | private |
implement(const ProGeOptions &options, std::vector< std::string > globalOptions, const std::vector< IDF::FUGenerated > &generatetFUs, const TTAMachine::Machine &machine, ProGe::NetlistBlock *core) | FUGen | static |
implementapleDAGs_ | FUGen | private |
implLatency_ | FUGen | private |
inferLSUSignal(const std::string &portName) const | FUGen | private |
isLSU_ | FUGen | private |
isLSUDataPort(const std::string &portName) | FUGen | private |
maxLatency_ | FUGen | private |
middleRegistered_ | FUGen | private |
minLatency_ | FUGen | private |
moduleName_ | FUGen | private |
netlistBlock_ | FUGen | private |
nodeImplementations_ | FUGen | private |
opcodeConstant(std::string operation) | FUGen | private |
opcodeSignal(int stage) | FUGen | private |
opcodeWidth_ | FUGen | private |
operandPlaceholder(int id) | FUGen | private |
operandSignal(std::string operation, int id) | FUGen | private |
operationCycles_ | FUGen | private |
operations_ | FUGen | private |
operator=(const FUGen &)=delete | FUGen | |
options_ | FUGen | private |
parseOperations() | FUGen | private |
pipelineLength_ | FUGen | private |
pipelineName(std::string port, int cycle) | FUGen | private |
pipelineValid(std::string port, int cycle) | FUGen | private |
portDirection_ | FUGen | private |
portInputs_ | FUGen | private |
prepareSnippet(std::string name, std::deque< std::string > statements, HDLGenerator::CodeBlock &sink, std::set< std::string > &addedStatements) | FUGen | private |
readFile(std::string filename) | FUGen | private |
readImplementation(std::string filename, std::string opName, std::deque< std::string > &sink) | FUGen | private |
registers_ | FUGen | private |
renamedGlobalSignals_ | FUGen | private |
renamedVariables_ | FUGen | private |
Replace typedef | FUGen | private |
replacesPerOp_ | FUGen | private |
replaceToken(std::string line, Replace replace) | FUGen | private |
resourceCount_ | FUGen | private |
resourceInputs_ | FUGen | private |
resourceOutputs_ | FUGen | private |
scheduledOperations_ | FUGen | private |
scheduleOperations() | FUGen | private |
selectedLanguage() | FUGen | private |
subOpConnection(OperationDAG *dag, OperationDAGEdge *edge, bool isOutput) | FUGen | private |
subOpCount_ | FUGen | private |
subOpName(OperationNode *node) | FUGen | private |
triggerPort_ | FUGen | private |
triggerSignal(int stage) | FUGen | private |
useGlock_ | FUGen | private |
useGlockRequest_ | FUGen | private |