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The user may specify constraints on maximal chip area, maximal power dissipation, minimal performance (of whole application, or of e.g. a critical loop within the application), and on maximal pin count. Based on these constraints the optimizer steers the software and hardware frameworks to produce valid architecture solutions. Although the MOVE framework severely restricts the allowable architecture solutions offered for a specific application, in practise the specified user constraints still leave a very large search space of allowable solutions.

The optimizer finds its way through this search space by iteratively trying different architecture solutions, and letting compiler and hardware framework produce relevant information about these solutions.

Ideally the user must be able to account costs to area, power dissipation, performance and pin count in such a way, that the optimizer finds its way in the architecture search space independent from further user input. This process can be very time consuming however, because many solutions must be processed by the software and hardware framework. The search time may be reduced by:

1. Using user knowledge. In practice we expect the user to be knowledgeable about the MOVE hardware and software frameworks, and is able to shorten the search trajectory to a satisfactory architecture solution, by interactively giving further hints (regarding changes to architecture parameters) to the optimizer. The user may be guided in this process by statistical information on solutions produced so far.
2. Using built-in knowledge. For certain architecture parameters, the software and hardware frameworks may be able to predict the influence of changing their values, without actually trying these changed values. These predictions can be used by the optimizer to cut off large parts of the search space.
3. Linear algorithms. In general, when iteratively a solution has to be found, it is essential keep the processing time per iteration minimal. Therefore software and hardware framework (in particular the code and processor layout generators) should aim at using algorithms which depend linear on the size of their input domain (like number of operations to be scheduled, or number of VLSI cells to position). In many cases however, linear algorithms are only possible in conjunction with smart heuristics.