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21 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
22 std::cerr <<
"\t\tPerforming late bypass guard: " <<
dst_.
toString() << std::endl;
27 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
28 std::cerr <<
"\t\t\tAborting guard bypass due too long guard distance" << std::endl;
35 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
36 std::cerr <<
"\t\t\tsrc src not op: "<<
src_.
toString() << std::endl;
43 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
44 std::cerr <<
"\t\t\tsrc not constant: " <<
dst_.
toString() << std::endl;
91 (fu == NULL || fu == gfu)) {
94 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
95 std::cerr <<
"\t\t\tFU: " << gfu->
name() <<
" not allowed for operation: " << po.
toString() << std::endl;
100 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
101 std::cerr <<
"\t\t\tFound suitable guard & FU" << std::endl;
117 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
118 std::cerr <<
"\t\tGuard conversion ok: " <<
dst_.
toString() << std::endl;
122 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
123 std::cerr <<
"\t\tGuard conversion sched fail.: " <<
dst_.
toString() << std::endl;
137 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
138 std::cerr <<
"\t\t\tDid not find a bus with suitable guard?" << std::endl;
148 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
149 std::cerr <<
"\t\t\tUndoing guard conversion: " <<
dst_.
toString() << std::endl;
157 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
158 std::cerr <<
"\t\t\tReassigning move: " <<
dst_.
toString() <<
" to cycle: "
163 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
164 std::cerr <<
"\t\tReassigned move:" <<
dst_.
toString() << std::endl;
const Operation & operation() const
std::stack< Reversible * > postChildren_
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
virtual TCEString name() const
std::string toString() const
FunctionUnit * parentUnit() const
bool isUnconditional() const
Terminal & destination() const
virtual bool operator()()
const TTAMachine::Bus & bus() const
void setGuard(MoveGuard *guard)
virtual void undoOnlyMe()
int outputIndexFromGuard(const TTAMachine::PortGuard &pg) const
virtual TCEString name() const
bool isLegalFU(const TTAMachine::FunctionUnit &fu) const
ProgramOperation & sourceOperation() const
#define assert(condition)
virtual int operationIndex() const
MoveGuard & guard() const
bool isSourceOperation() const
DataDependenceGraph & ddg()
virtual bool hasOperation(const std::string &name) const
int inputMoveCount() const
Guard * guard(int index) const
virtual void writeToDotFile(const TCEString &fileName) const
void guardRestored(MoveNode &guardSrc, MoveNode &dst)
int outputMoveCount() const
virtual const TTAMachine::FunctionUnit & functionUnit() const
TTAProgram::Move & move()
const TTAMachine::Guard * originalGuard_
std::string toString() const
virtual bool isInverted() const
void guardConverted(MoveNode &guardSrc, MoveNode &dst)
Terminal & source() const
const TTAMachine::Guard & guard() const
MoveNode & outputMove(int index) const
void setBus(const TTAMachine::Bus &bus)
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
MoveNode & inputMove(int index) const
const TTAMachine::Bus * originalBus_