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53 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
54 #define DEBUG_LOOP_SCHEDULER
65 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
66 std::cerr <<
"\t\tPerforming late bypass: " <<
dst_.
toString() <<std::endl;
68 #ifdef DEBUG_LOOP_SCHEDULER
70 std::cerr <<
"\t\tPerforming late bypass, dst: "
78 if (prologMN != NULL) {
80 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
81 std::cerr <<
"\t\t\t\tProlog move: " << prologMN->
toString()
83 std::cerr <<
"\t\t\t\tLate bypass saving prolog bus: "
99 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
100 std::cerr <<
"\t\t\tMerge and keep fail!" << std::endl;
111 writesJumpGuard(
dst_))) {
113 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
114 std::cerr <<
"Late bypass fail: must use originalcycle "
115 "which is too late!!!" << std::endl;
127 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
128 std::cerr <<
"\t\t\tToo long bypass dist, fail late bypass!"
138 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
139 std::cerr <<
"\t\tLate bypass ok: " <<
dst_.
toString() << std::endl;
143 for (
auto i : pred) {
149 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
150 std::cerr <<
"\t\tLate bypass sched fail.: " <<
dst_.
toString()
162 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
163 std::cerr <<
"\t\t\tUndoing late bypass: " <<
dst_.
toString() << std::endl;
166 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
167 std::cerr <<
"\t\t\tReassigning move: " <<
dst_.
toString() <<
" to cycle: "
171 std::cerr <<
"assign to original cycle fail, cycle: "
175 std::cerr <<
"\tDestination op: "
183 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
184 std::cerr <<
"\t\tReassigned move:" <<
dst_.
toString() << std::endl;
std::stack< Reversible * > postChildren_
virtual NodeSet predecessors(const Node &node, bool ignoreBackEdges=false, bool ignoreForwardEdges=false) const
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
bool isTriggering() const
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
virtual TCEString name() const
MoveNodeDuplicator & duplicator() const
std::string toString() const
std::set< MoveNode *, typename MoveNode ::Comparator > NodeSet
const TTAMachine::Bus & bus() const
#define assert(condition)
const TTAMachine::Bus * prologBus_
bool isGuardOperation() const
bool isControlFlowMove() const
virtual bool operator()()
DataDependenceGraph & ddg()
unsigned int destinationOperationCount() const
virtual void writeToDotFile(const TCEString &fileName) const
MoveNode * getMoveNode(MoveNode &mn)
ProgramOperation & destinationOperation(unsigned int index=0) const
TTAProgram::Move & move()
std::string toString() const
virtual void undoOnlyMe()
bool runPostChild(Reversible *preChild)
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
virtual void mightBeReady(MoveNode &mn)
const TTAMachine::Bus * originalBus_