OpenASIP
2.0
src
applibs
hdb
BlockImplementationFile.hh
Go to the documentation of this file.
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/*
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Copyright (c) 2002-2009 Tampere University.
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This file is part of TTA-Based Codesign Environment (TCE).
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*/
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/**
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* @file BlockImplementationFile.hh
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*
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* Declaration of BlockImplementationFile class.
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*
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* @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
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* @author Vinogradov Viacheslav(added Verilog generating) 2012
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* @note rating: red
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*/
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#ifndef TTA_BLOCK_IMPLEMENTATION_FILE_HH
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#define TTA_BLOCK_IMPLEMENTATION_FILE_HH
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#include <string>
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namespace
HDB
{
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/**
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* Represents a file that contains implementation for a block in HDB.
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*/
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class
BlockImplementationFile
{
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public
:
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/// Format of the file.
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enum
Format
{
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VHDL
,
///< VHDL file.
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Verilog
,
///< Verilog file.
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VHDLsim
,
///< VHDL simulation file.
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Verilogsim
///< Verilog simulation file.
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};
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BlockImplementationFile
(
const
std::string&
pathToFile
,
Format
format
);
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virtual
~BlockImplementationFile
();
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std::string
pathToFile
()
const
;
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Format
format
()
const
;
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void
setPathToFile
(
const
std::string&
pathToFile
);
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void
setFormat
(
Format
format
);
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private
:
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/// The file.
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std::string
file_
;
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/// Format of the file.
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Format
format_
;
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};
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}
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#endif
HDB
Definition:
CostDatabase.hh:49
HDB::BlockImplementationFile::setFormat
void setFormat(Format format)
Definition:
BlockImplementationFile.cc:92
HDB::BlockImplementationFile::VHDL
@ VHDL
VHDL file.
Definition:
BlockImplementationFile.hh:48
HDB::BlockImplementationFile::Format
Format
Format of the file.
Definition:
BlockImplementationFile.hh:47
HDB::BlockImplementationFile::~BlockImplementationFile
virtual ~BlockImplementationFile()
Definition:
BlockImplementationFile.cc:53
HDB::BlockImplementationFile::format_
Format format_
Format of the file.
Definition:
BlockImplementationFile.hh:67
HDB::BlockImplementationFile
Definition:
BlockImplementationFile.hh:44
HDB::BlockImplementationFile::file_
std::string file_
The file.
Definition:
BlockImplementationFile.hh:65
HDB::BlockImplementationFile::pathToFile
std::string pathToFile() const
Definition:
BlockImplementationFile.cc:61
HDB::BlockImplementationFile::Verilog
@ Verilog
Verilog file.
Definition:
BlockImplementationFile.hh:49
HDB::BlockImplementationFile::Verilogsim
@ Verilogsim
Verilog simulation file.
Definition:
BlockImplementationFile.hh:51
HDB::BlockImplementationFile::BlockImplementationFile
BlockImplementationFile(const std::string &pathToFile, Format format)
Definition:
BlockImplementationFile.cc:43
HDB::BlockImplementationFile::format
Format format() const
Definition:
BlockImplementationFile.cc:70
HDB::BlockImplementationFile::setPathToFile
void setPathToFile(const std::string &pathToFile)
Definition:
BlockImplementationFile.cc:81
HDB::BlockImplementationFile::VHDLsim
@ VHDLsim
VHDL simulation file.
Definition:
BlockImplementationFile.hh:50
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