41 Ext(std::string name,
int extWidth,
int signalWidth) {
43 if (extWidth > signalWidth) {
45 std::to_string(signalWidth));
51 Ext(std::string name, std::string extWidth,
int signalWidth) {
53 write_rtl(name, extWidth, std::to_string(signalWidth));
56 void write_rtl(std::string name, std::string extWidth,
57 std::string signalWidth) {
58 vhdl_ =
"((" + extWidth +
"-1 downto " + signalWidth
59 +
" => '0') & " + name +
")";
60 verilog_ =
"{{" + extWidth +
"-" + signalWidth +
"{"
61 +
"1'b0}}, " + name +
"}";
70 Splice(std::string name,
int upperBound,
int lowerBound) {
72 vhdl_ = name +
"(" + std::to_string(upperBound)
73 +
" downto " + std::to_string(lowerBound) +
")";
74 verilog_ = name +
"[" + std::to_string(upperBound)
75 +
":" + std::to_string(lowerBound) +
"]";
84 Sext(std::string name,
int extWidth,
int signalWidth) {
86 if (extWidth > signalWidth) {
87 write_rtl(name, std::to_string(extWidth), signalWidth);
94 Sext(std::string name, std::string extWidth,
int signalWidth) {
99 void write_rtl(std::string name, std::string extWidth,
101 std::string sigWidth = std::to_string(signalWidth);
102 vhdl_ =
"((" + extWidth +
"-1 downto " + sigWidth +
" => " + name;
103 verilog_ =
"{{" + extWidth +
"-" + sigWidth +
"{" + name +
"}";
104 if (signalWidth > 1) {
105 vhdl_ +=
"(" + sigWidth +
"-1)";
108 vhdl_ +=
") & " + name +
")";