OpenASIP  2.0
DefaultDecoderGenerator Member List

This is the complete list of members for DefaultDecoderGenerator, including all inherited members.

addGlockPortToDecoder()DefaultDecoderGeneratorprivate
addLockReqPortToDecoder()DefaultDecoderGeneratorprivate
bem_DefaultDecoderGeneratorprivate
busCntrlSignalPinOfSocket(const TTAMachine::Socket &socket, const TTAMachine::Bus &bus) constDefaultDecoderGeneratorprivate
busControlWidth(const TTAMachine::Socket &socket)DefaultDecoderGeneratorprivatestatic
busMuxCntrlRegister(const TTAMachine::Bus &bus)DefaultDecoderGeneratorprivatestatic
busMuxCntrlSignal(const TTAMachine::Bus &bus)DefaultDecoderGeneratorprivatestatic
busMuxEnableRegister(const TTAMachine::Bus &bus)DefaultDecoderGeneratorprivatestatic
busMuxEnableSignal(const TTAMachine::Bus &bus)DefaultDecoderGeneratorprivatestatic
BusSet typedefDefaultDecoderGeneratorprivate
completeDecoderBlock(const ProGe::NetlistGenerator &nlGenerator, ProGe::NetlistBlock &coreBlock)DefaultDecoderGenerator
connectedBuses(const TTAMachine::Socket &socket)DefaultDecoderGeneratorprivatestatic
containsSimilarGuard(const std::set< TTAMachine::PortGuard * > &guardSet, const TTAMachine::PortGuard &guard)DefaultDecoderGeneratorprivatestatic
containsSimilarGuard(const std::set< TTAMachine::RegisterGuard * > &guardSet, const TTAMachine::RegisterGuard &guard)DefaultDecoderGeneratorprivatestatic
dataControlWidth(const TTAMachine::Socket &socket)DefaultDecoderGeneratorprivatestatic
decoderBlock_DefaultDecoderGeneratorprivate
DefaultDecoderGenerator(const TTAMachine::Machine &machine, const BinaryEncoding &bem, const CentralizedControlICGenerator &icGenerator)DefaultDecoderGenerator
dstFieldSignal(const std::string &busName)DefaultDecoderGeneratorprivatestatic
entityNameStr_DefaultDecoderGeneratorprivate
findGuard(const GPRGuardEncoding &encoding) constDefaultDecoderGeneratorprivate
findGuard(const FUGuardEncoding &encoding) constDefaultDecoderGeneratorprivate
fuLoadCntrlPort(const std::string &fuName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
fuLoadSignalName(const std::string &fuName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
fuOpcodeCntrlPort(const std::string &fu)DefaultDecoderGeneratorprivatestatic
fuOpcodeSignalName(const std::string &fu)DefaultDecoderGeneratorprivatestatic
gcuDataPort(const std::string &nameInADF)DefaultDecoderGeneratorprivatestatic
generateAlternateGlockReqHandling_DefaultDecoderGeneratorprivate
generateBusEnable_DefaultDecoderGeneratorprivate
generateDebugger_DefaultDecoderGeneratorprivate
generateInstructionDecoder(const ProGe::NetlistGenerator &nlGenerator, const std::string &dstDirectory)DefaultDecoderGenerator
generateLockTrace_DefaultDecoderGeneratorprivate
GLOCK_PORT_NAMEDefaultDecoderGeneratorstatic
GlockBitType typedefDefaultDecoderGeneratorprivate
glockPortWidth() constDefaultDecoderGenerator
GlockReqBitType typedefDefaultDecoderGeneratorprivate
glockRequestWidth() constDefaultDecoderGenerator
guardFieldSignal(const std::string &busName)DefaultDecoderGeneratorprivatestatic
guardPortName(const TTAMachine::Guard &guard)DefaultDecoderGeneratorprivatestatic
icGenerator_DefaultDecoderGeneratorprivate
immSlotSignal(const std::string &immSlot)DefaultDecoderGeneratorprivatestatic
indentation(unsigned int level)DefaultDecoderGeneratorprivatestatic
instructionTemplateCondition(const ProGe::HDL language, const std::string &iTempName) constDefaultDecoderGeneratorprivate
iuReadLoadCntrlPort(const std::string &unitName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
iuReadLoadCntrlSignal(const std::string &unitName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
iuReadOpcodeCntrlPort(const std::string &unitName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
iuReadOpcodeCntrlSignal(const std::string &unitName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
iuWriteLoadCntrlPort(const std::string &unitName)DefaultDecoderGeneratorprivatestatic
iuWriteLoadCntrlSignal(const std::string &unitName)DefaultDecoderGeneratorprivatestatic
iuWriteOpcodeCntrlPort(const std::string &unitName)DefaultDecoderGeneratorprivatestatic
iuWriteOpcodeCntrlSignal(const std::string &unitName)DefaultDecoderGeneratorprivatestatic
iuWritePort(const std::string &iuName)DefaultDecoderGeneratorprivatestatic
iuWriteSignal(const std::string &iuName)DefaultDecoderGeneratorprivatestatic
language_DefaultDecoderGeneratorprivate
lockTraceStartingCycle_DefaultDecoderGeneratorprivate
machine_DefaultDecoderGeneratorprivate
moveFieldSignal(const std::string &busName)DefaultDecoderGeneratorprivatestatic
needsBusControl(const TTAMachine::Socket &socket)DefaultDecoderGeneratorprivatestatic
needsDataControl(const TTAMachine::Socket &socket)DefaultDecoderGeneratorprivatestatic
nlGenerator_DefaultDecoderGeneratorprivate
opcode(const TTAMachine::HWOperation &operation) constDefaultDecoderGeneratorprivate
opcodeWidth(const TTAMachine::FunctionUnit &fu) constDefaultDecoderGeneratorprivate
portCodeCondition(const ProGe::HDL language, const SocketEncoding &socketEnc, const PortCode &code)DefaultDecoderGeneratorprivatestatic
registerBitsDefaultDecoderGeneratorprivate
registerVectorsDefaultDecoderGeneratorprivate
requiredRFLatencies(const TTAMachine::ImmediateUnit &iu) constDefaultDecoderGenerator
rfLoadCntrlPort(const std::string &rfName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
rfLoadSignalName(const std::string &rfName, const std::string &portName, bool async=false)DefaultDecoderGeneratorprivatestatic
rfOpcodeCntrlPort(const std::string &rfName, const std::string &portName)DefaultDecoderGeneratorprivatestatic
rfOpcodeFromSrcOrDstField(const ProGe::HDL language, const SocketEncoding &socketEnc, const PortCode &code)DefaultDecoderGeneratorprivatestatic
rfOpcodeSignalName(const std::string &rfName, const std::string &portName, bool async=false)DefaultDecoderGeneratorprivatestatic
rfOpcodeWidth(const TTAMachine::BaseRegisterFile &rf)DefaultDecoderGeneratorprivatestatic
RISCV_SIMM_PORT_IN_NAMEDefaultDecoderGeneratorstatic
sacEnabled(const std::string &rfName) constDefaultDecoderGeneratorprivate
setGenerateBusEnable(bool value)DefaultDecoderGenerator
setGenerateDebugger(bool generate)DefaultDecoderGenerator
setGenerateLockTrace(bool generate)DefaultDecoderGenerator
setGenerateNoLoopbackGlock(bool generate)DefaultDecoderGenerator
SetHDL(ProGe::HDL language)DefaultDecoderGenerator
setLockTraceStartingCycle(unsigned int startCycle)DefaultDecoderGenerator
setSyncReset(bool value)DefaultDecoderGenerator
simmCntrlSignalName(const std::string &busName)DefaultDecoderGeneratorprivatestatic
simmControlPort(const std::string &busName)DefaultDecoderGeneratorprivatestatic
simmDataPort(const std::string &busName)DefaultDecoderGeneratorprivatestatic
simmDataSignalName(const std::string &busName)DefaultDecoderGeneratorprivatestatic
simmPortWidth(const TTAMachine::Bus &bus)DefaultDecoderGeneratorprivatestatic
socketBusCntrlSignalName(const std::string &name)DefaultDecoderGeneratorprivatestatic
socketBusControlPort(const std::string &name)DefaultDecoderGeneratorprivatestatic
socketDataCntrlSignalName(const std::string &name)DefaultDecoderGeneratorprivatestatic
socketDataControlPort(const std::string &name)DefaultDecoderGeneratorprivatestatic
socketEncodingCondition(const ProGe::HDL language, const SlotField &srcField, const std::string &socketName)DefaultDecoderGeneratorprivatestatic
squashSignal(const std::string &busName)DefaultDecoderGeneratorprivatestatic
srcFieldSignal(const std::string &busName)DefaultDecoderGeneratorprivatestatic
syncReset_DefaultDecoderGeneratorprivate
unitGlockBitMap_DefaultDecoderGeneratorprivate
UnitGlockBitMapType typedefDefaultDecoderGeneratorprivate
unitGlockReqBitMap_DefaultDecoderGeneratorprivate
UnitGlockReqBitMapType typedefDefaultDecoderGeneratorprivate
verifyCompatibility() constDefaultDecoderGenerator
writeBusControlRulesOfOutputSocket(const TTAMachine::Socket &socket, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeBusControlRulesOfSImmSocketOfBus(const TTAMachine::Bus &bus, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeBusMuxControlLogic(const TTAMachine::Bus &bus, const std::set< TTAMachine::Socket * > outputSockets, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeComment(std::ostream &stream, int indent, std::string comment) constDefaultDecoderGeneratorprivate
writeControlRegisterMappings(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeControlRulesOfFUInputPort(const TTAMachine::BaseFUPort &port, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeControlRulesOfFUOutputPort(const TTAMachine::BaseFUPort &port, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeControlRulesOfRFReadPort(const TTAMachine::RFPort &port, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeControlRulesOfRFWritePort(const TTAMachine::RFPort &port, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeDismemberingAndITDecompression(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeFUCntrlSignals(std::ostream &stream)DefaultDecoderGeneratorprivate
writeFUCntrlSignals(const TTAMachine::FunctionUnit &fu, std::ostream &stream)DefaultDecoderGeneratorprivate
writeFullNOPConstant(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeGlockHandlingSignals(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeGlockMapping(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeImmediateSlotSignals(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeInstructionDecoder(std::ostream &stream)DefaultDecoderGeneratorprivate
writeInstructionDecoding(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeInstructionDismembering(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeInstructionTemplateProcedures(const ProGe::HDL language, const TTAMachine::InstructionTemplate &iTemp, int indLevel, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeLockDumpCode(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeLongImmediateTagSignal(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeLongImmediateWriteProcess(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeMainDecodingProcess(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeMoveFieldSignals(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeNOPEncodingVHDL() constDefaultDecoderGeneratorprivate
writePipelineFillProcess(std::ostream &stream) constDefaultDecoderGeneratorprivate
writePipelineFillSignals(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeResettingOfControlRegisters(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeRFCntrlSignals(std::ostream &stream)DefaultDecoderGeneratorprivate
writeRFSRAMDecodingProcess(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeRulesForDestinationControlSignals(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeRulesForSourceControlSignals(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeSignalDeclaration(std::ostream &stream, ProGe::DataType type, std::string sigName, int width) constDefaultDecoderGeneratorprivate
writeSimmDataSignal(const TTAMachine::Bus &bus, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeSocketCntrlSignals(std::ostream &stream)DefaultDecoderGeneratorprivate
writeSquashSignalGenerationProcess(const TTAMachine::Bus &bus, std::ostream &stream) constDefaultDecoderGeneratorprivate
writeSquashSignalGenerationProcesses(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeSquashSignals(std::ostream &stream) constDefaultDecoderGeneratorprivate
writeSquashSignalSubstitution(const ProGe::HDL language, const TTAMachine::Bus &bus, const GuardEncoding &enc, const TTAMachine::Guard &guard, std::ostream &stream, int indLevel)DefaultDecoderGeneratorprivatestatic
~DefaultDecoderGenerator()DefaultDecoderGeneratorvirtual
Generated by   doxygen 1.8.17