Customized Parallel
Computing (CPC) group

This is the home page of the CPC research group of Tampere University. The group's name in Finnish is Räätälöity rinnakkaislaskenta. CPC's main research focus is on design and programming methodologies of customized parallel computing platforms and real time implementations of challenging algorithms.


In addition to publications and theses listed here as academic contributions, CPC has also made major open source contributions in the field of portable and customized heterogeneous computing: The group has created OpenASIP and Portable Computing Language (pocl) which are being used widely as research platforms and even for product use cases. CPC also created the prototype HIPCL tool which evolved into chipStar, a portable CUDA/HIP implementation using open standards.


An algorithm domain with extreme computational demands that CPC has been very interested in the past years is real time ray tracing. A separate focus group was formed for finding algorithmic, parallel/heterogeneous implementation and custom hardware solutions for its challenges in 2015. The group's web pages are here.



News

September 5th, 2025: PoCL-R journal extension published

Modern mobile devices execute intensive tasks with limited compute resources. Offloading these tasks over networks to more capable devices such as a server is appealing, but the overheads of communication can easily mitigate the benefits. Ideally, a task described with one input language can be offloaded to a number of heterogeneous computing platforms. Our article published in The International Journal of High Performance Computing Applications describes how Pocl-R allows low-latency, robust offloading of OpenCL programs over networks. The article is available here.

PoCL-R stack

July 7th, 2025: New publication added

Population ageing is a global societal challenge. The increasing proportion of elderly people of the population comes with increases in healthcare costs. Smart-health cyber-physical (CPS) systems are an approach to alleviate these costs. In collaboration with University of Granada, we propose a framework for monitoring and producing alarms in the context of indoor ambient assisted living for the elderly. The article is titled "Efficient reconfigurable system for home monitoring of the elderly via action recognition" and is available (here).

June 2nd, 2025: Two new publications and two masters theses added
  • Jan Solanti, Pekka Jääskeläinen:
    "Latency Reduction Potential of Server-Side Command Buffers in OpenCL-Based Edge Offloading",
    in in the 13th International Workshop on OpenCL and SYCL (IWOCL), Apr. 2025 (download).
  • Jakub Žádník, Robin Bijl and Jan Solanti, Erno Joensuu, Markku Mäkitalo and Pekka Jääskeläinen:
    "Open Software Stack for Compression-Aware Adaptive Edge Offloading",
    in in IEEE Wireless Communications and Networking Conference (WCNC), Mar. 2025 (download).
    • Antti Hahka:
      "Physical Safety in Wireless Edge Offloading of Control Decisions: A case study using a nano-drone"
      (2024) (link)
    • Yashvardhan Agarwal:
      "Dynamic Device Management and Automatic Network Resource Discovery in OpenCL for Multi-Access Edge Computing"
      (2024) (link)
    Apr 29th, 2025: Server side command buffers for efficient OpenCL offloading at IWOCL '25

    Our doctoral researcher Jan Solanti presented the paper "Latency Reduction Potential of Server-Side Command Buffers in OpenCL-Based Edge Offloading" at IWOCL '25. Command buffers provide applications with a simple way to reduce API overhead from identically repeated workloads, as well as a natural point for OpenCL runtimes to perform optimizations and e.g. submit commands as a batch. We demonstrate this utility of command buffers with a server-side implementation of command buffers in PoCL-Remote, which will be available in the upcoming PoCL 7.0 release.

    Jan at IWOCL 2025

    You can watch the presentation below:
    Mar 24th, 2025: CPC participates in the DARE project

    The DARE project aims to advance European sovereignty in high-performance computing (HPC). The project designs and develops a general-purpose processor targeted to run major HPC workloads as well as two accelerators: A vector accelerator and an AI processing unit. On the hardware side, CPC is participating in DARE by researching coherent caches in the context of HPC. An efficient memory hierarchy is critical for the manycore processors used in HPC systems as providing data and enabling smooth synchronization can be become a bottleneck for performance. CPC also participates in developing a heterogeneous parallel computing software stack based on PoCL, ChipStar and SYCL with GROMACS as the optimized example HPC application. The project kickoff meeting was held on 10-11 March 2025 in Barcelona, where we were happy to meet great minds from both the academia and industry!
    Links:

    DARE kickoff group photo


    (older news here)

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