OpenASIP 2.2
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BlockImplementationFile.hh
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1/*
2 Copyright (c) 2002-2009 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file BlockImplementationFile.hh
26 *
27 * Declaration of BlockImplementationFile class.
28 *
29 * @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
30 * @author Vinogradov Viacheslav(added Verilog generating) 2012
31 * @note rating: red
32 */
33
34#ifndef TTA_BLOCK_IMPLEMENTATION_FILE_HH
35#define TTA_BLOCK_IMPLEMENTATION_FILE_HH
36
37#include <string>
38
39namespace HDB {
40
41/**
42 * Represents a file that contains implementation for a block in HDB.
43 */
45public:
46 /// Format of the file.
47 enum Format {
48 VHDL, ///< VHDL file.
49 Verilog, ///< Verilog file.
50 VHDLsim, ///< VHDL simulation file.
51 Verilogsim ///< Verilog simulation file.
52 };
53
56
57 std::string pathToFile() const;
58 Format format() const;
59
60 void setPathToFile(const std::string& pathToFile);
62
63private:
64 /// The file.
65 std::string file_;
66 /// Format of the file.
68};
69}
70
71#endif
@ Verilogsim
Verilog simulation file.
Format format_
Format of the file.
void setPathToFile(const std::string &pathToFile)