OpenASIP 2.2
Loading...
Searching...
No Matches
TCEStubTargetMachine.cc
Go to the documentation of this file.
1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23*/
24/**
25 * @file TCEStubTargeMachine.cc
26 *
27 * Declaration of TCEStubTargetMachine class.
28 *
29 * @author Ville Korhonen 2015
30 */
31
32/**
33 * This Stub target is for middle end optimizations where the actual backend
34 * plugin is not yet generated.
35 *
36 * Intention is to use ADF information in
37 * targetTransformInfo class to offer target spesific details for middle end
38 * optimizations such as loop vectorizer.
39 *
40 * @todo pass for handing over the ADF to the stub target.
41 * @todo add more target spesific features to targetTransformInfo
42 * @todo unify TCEStubTarget and TCETarget features by migrating common
43 * features to base class
44 */
45
46#include "CompilerWarnings.hh"
47IGNORE_COMPILER_WARNING("-Wunused-parameter")
48
49#include "tce_config.h"
51#include "ADFSerializer.hh"
53#include "TCEStubSubTarget.hh"
54#include <llvm/Target/TargetLoweringObjectFile.h>
55#include <llvm/Target/TargetMachine.h>
56#include <llvm/CodeGen/Passes.h>
57#include <llvm/IR/LegacyPassManager.h>
58#include <llvm/Target/TargetOptions.h>
59#include <llvm/CodeGen/TargetPassConfig.h>
60
61using namespace llvm;
62
66
67extern "C" void LLVMInitializeTCETargetInfo() {
68 RegisterTarget<Triple::tce, /*HasJIT=*/false>
69 X(TheTCETarget, "tce-tut-llvm", "TCE custom processor",
70 "TODO: wonder what this button does");
71 RegisterTarget<Triple::tcele, false>
72 Y(TheTCELETarget, "tcele-tut-llvm",
73 "TCE custom processor (little endian)",
74 "TODO: wonder what this button does");
75 RegisterTarget<Triple::tcele64, false>
76 Z(TheTCELE64Target, "tcele64-tut-llvm", "64-bit TCE custom processor (little endian) ",
77 "TODO: wonder what this button does");
78}
79
80extern "C" void LLVMInitializeTCEStubTarget() {
81 // Register the targetmachine impl.
82 RegisterTargetMachine<TCEStubTargetMachine> X(TheTCETarget);
83 RegisterTargetMachine<TCEStubTargetMachine> Y(TheTCELETarget);
84 RegisterTargetMachine<TCEStubTargetMachine> Z(TheTCELE64Target);
85}
86
88
89StringRef DescriptionStringBE = "E-p:32:32:32-i1:8:8-i8:8:32-"
90 "i16:16:32-i32:32:32-i64:32:32-"
91 "f32:32:32-f64:32:32-v64:32:32-"
92 "v128:32:32-v256:32:32-v512:32:32-v1024:32:32-a0:0:32-n32";
93
94#if LLVM_HAS_CUSTOM_VECTOR_EXTENSION == 2
95StringRef DescriptionStringLE = "e-p:32:32:32-i1:8:8-i8:8:32-"
96 "i16:16:32-i32:32:32-i64:32:32-"
97 "f32:32:32-f64:32:32-v64:64:64-"
98 "v128:128:128-v256:256:256-v512:512:512-v1024:1024:1024-"
99 "v2048:2048:2048-v4096:4096:4096-a0:0:32-n32";
100#else
101StringRef DescriptionStringLE = "e-p:32:32:32-i1:8:8-i8:8:32-"
102 "i16:16:32-i32:32:32-i64:32:32-"
103 "f32:32:32-f64:32:32-v64:64:64-"
104 "v128:128:128-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:32-n32";
105#endif
106
107StringRef DescriptionStringLE64 = "e-p:64:64:64-i1:8:64-i8:8:64-"
108 "i16:16:64-i32:32:64-i64:64:64-"
109 "f32:32:64-f64:64:64-v64:64:64-"
110 "v128:128:128-v256:256:256-v512:512:512-v1024:1024:1024-"
111 "v2048:2048:2048-v4096:4096:4096-a0:0:64-n64";
112
113StringRef getTargetDesc(const Triple &TT) {
114 if (TT.getArchName().equals("tce"))
115 return DescriptionStringBE;
116 else {
117 if (TT.getArchName().equals("tcele"))
118 return DescriptionStringLE;
119 else
121 }
122}
123
124/* Base class constructor */
126 const Target &T, const Triple& TT, const llvm::StringRef& CPU,
127 const llvm::StringRef& FS, const TargetOptions &Options,
128 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) :
129 LLVMTargetMachine(T, getTargetDesc(TT), TT, CPU, FS, Options, RM, CM, OL),
130 ttaMach_(NULL) {
131}
132
133
135 const Target &T, const Triple &TT, const llvm::StringRef& CPU,
136 const llvm::StringRef& FS, const TargetOptions &Options,
137 #ifdef LLVM_OLDER_THAN_16
138 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
139 #else
140 std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM,
141 #endif
142 CodeGenOpt::Level OL, bool) :
143 TCEBaseTargetMachine(T, TT, CPU, FS, Options,
144 RM?*RM:Reloc::Model::Static,
145 CM?*CM:CodeModel::Small, OL),
146 // Note: Reloc::Model does not have "Default" named member. "Static" is ok?
147 // Note: CodeModel does not have "Default" named member. "Small" is ok?
148 TLOF(new TargetLoweringObjectFileELF) {
149// TLOF(new TargetLoweringObjectFile) {
150 ST = new TCEStubSubTarget(TT, CPU, FS, *this);
151
152 // For autovectorization to work we need to set target machine information:
153 auto* option = static_cast<llvm::cl::opt<std::string>*>(
154 llvm::cl::getRegisteredOptions().lookup("adf"));
155 const std::string adfName = option->getValue();
156
157 ADFSerializer serializer;
158 if (adfName == "") {
159 const std::string msg = "ADF not passed to opt,"
160 "make sure it is included in oacc";
161 throw CompileError(__FILE__, __LINE__, __func__, msg);
162 }
163
164 serializer.setSourceFile(adfName);
165 // Create and set TTAMachine
166 TTAMachine::Machine* targetTTAMachine = serializer.readMachine();
167 setTTAMach(targetTTAMachine);
168}
169
171
172namespace {
173 /**
174 * Minimalistic pass config for middle end passes
175 */
176 class TCEStubPassConfig : public TargetPassConfig {
177 public:
178 TCEStubPassConfig(TCEStubTargetMachine *TM, PassManagerBase &PM)
179 : TargetPassConfig(*TM, PM) {}
180
181 TCEStubTargetMachine &getTCEStubTargetMachine() const {
182 return getTM<TCEStubTargetMachine>();
183 }
184
185 };
186} // end namespace
#define __func__
#define IGNORE_COMPILER_WARNING(X)
static llvm::RegisterPass< InnerLoopFinder > X("find-innerloops-test", "Finds inner loops test.", false, true)
StringRef DescriptionStringLE
void LLVMInitializeTCETargetInfo()
StringRef DescriptionStringBE
void LLVMInitializeTCEStubTargetMC()
void LLVMInitializeTCEStubTarget()
StringRef getTargetDesc(const Triple &TT)
StringRef DescriptionStringLE64
TTAMachine::Machine * readMachine()
Definition Model.hh:50
void setSourceFile(const std::string &fileName)
TCEBaseTargetMachine(const Target &T, const Triple &TT, const llvm::StringRef &CPU, const llvm::StringRef &FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
virtual void setTTAMach(const TTAMachine::Machine *mach)
TCEStubTargetMachine(const Target &T, const Triple &TT, const llvm::StringRef &CPU, const llvm::StringRef &FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Target TheTCETarget
Target TheTCELETarget
Target TheTCELE64Target