OpenASIP 2.2
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TTASimulationController.hh
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1/*
2 Copyright (c) 2002-2012 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file CompiledSimController.hh
26 *
27 * Declaration of TTASimulationController class.
28 *
29 * @author Viljami Korhonen 2008 (viljami.korhonen-no.spam-tut.fi)
30 * @note rating: red
31 */
32
33#ifndef TTA_SIMULATION_CONTROLLER_HH
34#define TTA_SIMULATION_CONTROLLER_HH
35
36#include <set>
37#include <vector>
38
39#include "Exception.hh"
40#include "BaseType.hh"
41#include "SimulatorConstants.hh"
43
44class MemorySystem;
45class MachineState;
47class GCUState;
48class IllegalMachine;
49class SimValue;
51class StateData;
52class MemorySystem;
53class Memory;
55
56namespace TTAMachine {
57 class Machine;
58}
59
60namespace TTAProgram {
61 class Program;
62}
63
64/**
65 * An abstract interface class for controlling the simulation
66 *
67 * Owns and is the main client of the machine state model.
68 */
70public:
71 /// The states of simulation.
73 STA_INITIALIZING,///< Simulation is being initialized.
74 STA_INITIALIZED, ///< Simulation initialized and ready to run.
75 STA_RUNNING, ///< A run command (run, stepi, until...) given.
76 STA_STOPPED, ///< Simulation stopped for some reason.
78 ///< Simulation ended after executing the last instruction.
79 };
80
85
87
88 virtual void step(double count = 1) = 0;
89
90 virtual void next(int count = 1) = 0;
91
92 virtual void run() = 0;
93
94 virtual void runUntil(UIntWord address) = 0;
95
96 virtual void reset() = 0;
97
98
99 virtual std::string registerFileValue(
100 const std::string& rfName,
101 int registerIndex = -1) = 0;
102
104 const std::string& iuName, int index = -1) = 0;
105
107 const std::string& fuName,
108 const std::string& portName) = 0;
109
110 virtual void prepareToStop(StopReason reason);
111 virtual unsigned int stopReasonCount() const;
112 virtual StopReason stopReason(unsigned int index) const;
113 virtual SimulationStatus state() const;
115 virtual InstructionAddress lastExecutedInstruction(int coreId=-1) const;
116 virtual ClockCycleCount clockCount() const;
117 virtual MemorySystem& memorySystem(int coreId=-1);
118 virtual SimulatorFrontend& frontend();
119 virtual bool automaticFinishImpossible() const;
120
121 virtual std::set<InstructionAddress> findProgramExitPoints(
123 const TTAMachine::Machine& machine) const;
124
125protected:
126 /// Copying not allowed.
128 /// Assignment not allowed.
130
131 /// The container type for reasons why simulation stop was requested.
132 typedef std::set<StopReason> StopReasonContainer;
133
134 /// Reference to the simulator frontend
136 /// The simulated Machine Object Model.
138 /// Program object model of the simulated program.
140
141 /// Flag indicating that simulation should stop.
143 /// The set of reasons the simulation was stopped.
145
146 /// The current state of the simulation.
148 /// How many clock cycles have been simulated.
150 /// The address of the last executed instruction.
151 std::vector<InstructionAddress> lastExecutedInstruction_;
152 /// The address of the first executed instruction.
154 /// If this is true, simulation cannot be finished automatically.
156 /// The index of the first illegal instruction in the instruction
157 /// sequence.
159};
160
161#endif
Word UIntWord
Definition BaseType.hh:144
UInt32 InstructionAddress
Definition BaseType.hh:175
TTAMachine::Machine * machine
the architecture definition of the estimated processor
find Finds info of the inner loops in the program
CycleCount ClockCycleCount
Alias for ClockCycleCount.
StopReason
The reasons to stop simulation.
InstructionAddress initialPC_
The address of the first executed instruction.
StopReasonContainer stopReasons_
The set of reasons the simulation was stopped.
virtual StopReason stopReason(unsigned int index) const
virtual SimValue FUPortValue(const std::string &fuName, const std::string &portName)=0
TTASimulationController(const TTASimulationController &)
Copying not allowed.
virtual bool automaticFinishImpossible() const
const TTAMachine::Machine & sourceMachine_
The simulated Machine Object Model.
virtual void step(double count=1)=0
virtual void reset()=0
std::vector< InstructionAddress > lastExecutedInstruction_
The address of the last executed instruction.
virtual unsigned int stopReasonCount() const
bool stopRequested_
Flag indicating that simulation should stop.
virtual SimulationStatus state() const
virtual void prepareToStop(StopReason reason)
SimulationStatus
The states of simulation.
@ STA_FINISHED
Simulation ended after executing the last instruction.
@ STA_INITIALIZING
Simulation is being initialized.
@ STA_RUNNING
A run command (run, stepi, until...) given.
@ STA_STOPPED
Simulation stopped for some reason.
@ STA_INITIALIZED
Simulation initialized and ready to run.
virtual SimulatorFrontend & frontend()
virtual std::set< InstructionAddress > findProgramExitPoints(const TTAProgram::Program &program, const TTAMachine::Machine &machine) const
virtual std::string registerFileValue(const std::string &rfName, int registerIndex=-1)=0
virtual void next(int count=1)=0
std::set< StopReason > StopReasonContainer
The container type for reasons why simulation stop was requested.
InstructionAddress firstIllegalInstructionIndex_
The index of the first illegal instruction in the instruction sequence.
virtual void runUntil(UIntWord address)=0
virtual InstructionAddress lastExecutedInstruction(int coreId=-1) const
const TTAProgram::Program & program_
Program object model of the simulated program.
SimulationStatus state_
The current state of the simulation.
virtual ClockCycleCount clockCount() const
bool automaticFinishImpossible_
If this is true, simulation cannot be finished automatically.
TTASimulationController & operator=(const TTASimulationController &)
Assignment not allowed.
ClockCycleCount clockCount_
How many clock cycles have been simulated.
virtual SimValue immediateUnitRegisterValue(const std::string &iuName, int index=-1)=0
virtual void run()=0
SimulatorFrontend & frontend_
Reference to the simulator frontend.
virtual InstructionAddress programCounter() const =0
virtual MemorySystem & memorySystem(int coreId=-1)