59 context_(&parent.context()),
60 tempContext_(NULL, PC_, RA_, parent.context().branchDelayCycles()),
102 for (
int i = 0; i < operands; ++i)
#define assert(condition)
virtual OperationContext & context()
void setReturnAddress(const InstructionAddress &value)
void setProgramCounter(const InstructionAddress &value)
void setSaveReturnAddress(bool value)
void setUpdateProgramCounter(bool value)
bool updateProgramCounter() const
void setStateRegistry(StateRegistry &stateRegistry)
StateRegistry & stateRegistry()
void unsetStateRegistry()
SimValue & returnAddress()
InstructionAddress & programCounter()
PortState & binding(int io) const
virtual bool isCall() const
virtual bool isBranch() const
virtual bool simulateTrigger(SimValue **, OperationContext &context) const
virtual int numberOfInputs() const
virtual int numberOfOutputs() const
virtual ~TransportPipeline()
GCUState & parent_
The owner GCUState.
virtual void setContext(OperationContext &context)
virtual void startOperation(Operation &op)
OperationContext * context_
Operation context used to fetch the values for PC and RA.
Operation * operation_
Operation to be triggered next.
OperationContext tempContext_
Operation context seen by the operation.
virtual void advanceClock()
virtual int latency() const
TransportPipeline(GCUState &parent)
virtual OperationExecutor * copy()