OpenASIP 2.2
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TransportPipeline.cc
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1/*
2 Copyright (c) 2002-2009 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file TransportPipeline.cc
26 *
27 * Definition of TransportPipeline class.
28 *
29 * @author Jussi Nykänen 2004 (nykanen-no.spam-cs.tut.fi)
30 * @author Pekka Jääskeläinen 2005,2009 (pjaaskel-no.spam-cs.tut.fi)
31 * @note rating: red
32 */
33
34#include <vector>
35
36#include "TransportPipeline.hh"
37#include "SimValue.hh"
38#include "FUState.hh"
39#include "Operation.hh"
40#include "Application.hh"
41#include "OperationContext.hh"
42#include "Operation.hh"
43#include "GCUState.hh"
44#include "SimulatorToolbox.hh"
45#include "OperationPool.hh"
46#include "StringTools.hh"
47#include "TCEString.hh"
48
49using std::vector;
50using std::string;
51
52/**
53 * Constructor.
54 *
55 * @param parent Parent of the pipeline.
56 */
58 OperationExecutor(parent), operation_(NULL),
59 context_(&parent.context()),
60 tempContext_(NULL, PC_, RA_, parent.context().branchDelayCycles()),
61 parent_(parent) {
62 // delete the own state registry to avoid mem leaks
64 // share the state registry with the actual context
66}
67
68/**
69 * Destructor.
70 */
74
75/**
76 * Returns the latency of the pipeline.
77 *
78 * @return The latency of the pipeline.
79 */
80int
82 return 0;
83}
84
85/**
86 * Start the execution of the operation.
87 *
88 * First inputs and outputs of the operation are collected in a vector.
89 * Then a new operation context is created. After triggering the operation
90 * the registers which values are changed are updated in parent GCU state.
91 *
92 * @param op Operation to be triggered.
93 * @todo This can be optimized a lot.
94 */
95void
97
98 operation_ = &op;
99 int operands = op.numberOfInputs() + op.numberOfOutputs();
100 SimValue* io[32];
101 assert(operands < 32);
102 for (int i = 0; i < operands; ++i)
103 io[i] = const_cast<SimValue*>(&(binding(i + 1).value()));
104
105 // use a temporary context here as the original context points to the
106 // internal program counter variables of the simulator engine,
107 // which we do not want to modify in the middle of simulating
108 // a cycle
114
115 // If the operation is a jump or a call operation, update the program
116 // counter after delay slot cycles. If a loop buffer setup op is called,
117 // do not update the program counter this way.
118 if (tempContext_.updateProgramCounter() && (op.isCall() || op.isBranch())) {
120 }
123 }
124}
125
126/**
127 * Nothing is done when clock cycle changes.
128 */
129void
132
133/**
134 * Copies OperationExecutor.
135 *
136 * @return The copied OperationExecutor.
137 */
140 return new TransportPipeline(*this);
141}
142
143/**
144 * Sets the OperationContext of the pipeline.
145 *
146 * @param context The OperationContext.
147 */
148void
152
#define assert(condition)
virtual OperationContext & context()
Definition FUState.cc:376
void setReturnAddress(const InstructionAddress &value)
void setProgramCounter(const InstructionAddress &value)
void setSaveReturnAddress(bool value)
void setUpdateProgramCounter(bool value)
bool updateProgramCounter() const
void setStateRegistry(StateRegistry &stateRegistry)
StateRegistry & stateRegistry()
SimValue & returnAddress()
InstructionAddress & programCounter()
PortState & binding(int io) const
FUState & parent() const
virtual bool isCall() const
Definition Operation.cc:318
virtual bool isBranch() const
Definition Operation.cc:306
virtual bool simulateTrigger(SimValue **, OperationContext &context) const
Definition Operation.cc:555
virtual int numberOfInputs() const
Definition Operation.cc:192
virtual int numberOfOutputs() const
Definition Operation.cc:202
GCUState & parent_
The owner GCUState.
virtual void setContext(OperationContext &context)
virtual void startOperation(Operation &op)
OperationContext * context_
Operation context used to fetch the values for PC and RA.
Operation * operation_
Operation to be triggered next.
OperationContext tempContext_
Operation context seen by the operation.
virtual void advanceClock()
virtual int latency() const
TransportPipeline(GCUState &parent)
virtual OperationExecutor * copy()