OpenASIP 2.2
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VhdlImageWriter.cc
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1/*
2 Copyright (c) 2002-2010 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file VhdlImageWriter.cc
26 *
27 * Implementation of VhdlImageWriter class.
28 *
29 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30 * @note rating: red
31 */
32
33#include <iostream>
35#include "ArrayImageWriter.hh"
36#include "VhdlImageWriter.hh"
37using std::endl;
38
39/**
40 * The constructor.
41 *
42 * @param bits The bits to write.
43 * @param rowLength Length of the rows to write.
44 */
46 const BitVector& bits,
47 int rowLength,
48 const std::string& entityName) :
49 ArrayImageWriter(bits, rowLength), entityName_(entityName) {
50}
51
52/**
53 * The destructor.
54 */
57
58/**
59 * Writes the bit image to the given stream.
60 *
61 * @param stream The stream to write.
62 */
63void VhdlImageWriter::writeImage(std::ostream& stream) const {
64 writeHeader(stream);
66 writeEnding(stream);
67}
68
69
70/**
71 * Writes the vhdl declaration stuff to the beginning of the stream
72 */
73void VhdlImageWriter::writeHeader(std::ostream& stream) const {
74 stream << "library ieee;" << endl
75 << "use ieee.std_logic_1164.all;" << endl
76 << "use ieee.std_logic_arith.all;" << endl << endl;
77
78 stream << "package " << packageName() << " is" << endl << endl
79 << " type std_logic_dmem_matrix is array (natural range <>) of "
80 << "std_logic_vector(" << rowLength() << "-1 downto 0);"
81 << endl << endl;
82
83 stream << " constant dmem_array : std_logic_dmem_matrix := (" << endl;
84}
85
86/**
87 * Writes the end declarations to the stream
88 */
89void VhdlImageWriter::writeEnding(std::ostream& stream) const {
90 stream << ");" << endl << endl
91 << "end " << packageName() << ";" << endl;
92}
93
94std::string
96
97 std::string package = "dmem_image";
98 if (!entityName_.empty()) {
99 package = entityName_ + "_" + package;
100 }
101 return package;
102}
virtual void writeImage(std::ostream &stream) const
std::string packageName() const
VhdlImageWriter(const BitVector &bits, int rowLength, const std::string &entityName)
virtual void writeImage(std::ostream &stream) const
void writeHeader(std::ostream &stream) const
void writeEnding(std::ostream &stream) const
virtual ~VhdlImageWriter()