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54 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
55 std::cerr <<
"\t\t\tCannot reschedule control flow move!" << std::endl;
61 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
62 std::cerr <<
"\t\t|TCannot reschedule guard write move!" << std::endl;
80 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
81 std::cerr <<
"\t\t\t\t\ttopdown resched: " << ec << std::endl;
89 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
90 std::cerr <<
"\t\t\t\tbottomup resched ddglc: " << ddgLC <<
" latest_: "
94 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
95 std::cerr <<
"\t\tPushing down antidep dest: " <<
mn_.
toString()
96 <<
" failed lc: "<< lc <<
" ddgEC: " << ddgEC << std::endl;
97 std::cerr <<
"\t\tPushAntidepsDown seting to old bus: "
101 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
110 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
111 std::cerr <<
"\t\tPushed antidep down: " <<
mn_.
toString() <<
" bus: "
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
virtual TCEString name() const
std::string toString() const
const TTAMachine::Bus * oldBus_
const TTAMachine::Bus & bus() const
virtual int rmEC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
#define assert(condition)
bool isControlFlowMove() const
DataDependenceGraph & ddg()
int earliestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegWaRs=false, bool ignoreRegWaWs=false, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false, bool assumeBypassing=false) const
void unscheduleOriginal()
TTAProgram::Move & move()
const TTAMachine::Bus * prologBus_
virtual int rmLC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
MoveNode * guardWriteNode()
int maximumAllowedCycle() const
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
int latestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegAntideps=false, bool ignoreUnscheduledSuccessors=true, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false) const