54#ifdef DEBUG_BUBBLEFISH_SCHEDULER
55 std::cerr <<
"\t\t\tCannot reschedule control flow move!" << std::endl;
61#ifdef DEBUG_BUBBLEFISH_SCHEDULER
62 std::cerr <<
"\t\t|TCannot reschedule guard write move!" << std::endl;
80#ifdef DEBUG_BUBBLEFISH_SCHEDULER
81 std::cerr <<
"\t\t\t\t\ttopdown resched: " << ec << std::endl;
89#ifdef DEBUG_BUBBLEFISH_SCHEDULER
90 std::cerr <<
"\t\t\t\tbottomup resched ddglc: " << ddgLC <<
" latest_: "
94#ifdef DEBUG_BUBBLEFISH_SCHEDULER
95 std::cerr <<
"\t\tPushing down antidep dest: " <<
mn_.
toString()
96 <<
" failed lc: "<< lc <<
" ddgEC: " << ddgEC << std::endl;
97 std::cerr <<
"\t\tPushAntidepsDown seting to old bus: "
101#ifdef DEBUG_BUBBLEFISH_SCHEDULER
110#ifdef DEBUG_BUBBLEFISH_SCHEDULER
111 std::cerr <<
"\t\tPushed antidep down: " <<
mn_.
toString() <<
" bus: "
#define assert(condition)
int maximumAllowedCycle() const
MoveNode * guardWriteNode()
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
DataDependenceGraph & ddg()
virtual int rmLC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
virtual int rmEC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
const TTAMachine::Bus * prologBus_
void unscheduleOriginal()
const TTAMachine::Bus * oldBus_
int latestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegAntideps=false, bool ignoreUnscheduledSuccessors=true, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false) const
int earliestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegWaRs=false, bool ignoreRegWaWs=false, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false, bool assumeBypassing=false) const
std::string toString() const
TTAProgram::Move & move()
virtual TCEString name() const
bool isControlFlowMove() const
const TTAMachine::Bus & bus() const