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66 if (prologMN != NULL) {
73 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
74 std::cerr <<
"\t\t\t\tProlog move: " << prologMN->
toString() << std::endl;
75 std::cerr <<
"\t\t\t\tBFUnscheduleMove Saving prolog bus: " <<
prologBus_->
name() <<
" cycle: " <<
oldCycle_ << std::endl;
78 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
85 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
91 std::cerr <<
"\t\tCannot assign to old cycle: " <<
mn_.
toString()
92 <<
" old cycle: " <<
oldCycle_ << std::endl;
108 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
112 std::cerr <<
"\t\treturning original: " <<
mn_.
toString() <<
" current bus: "
117 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
121 std::cerr <<
"Cannot return to old cycle: " <<
mn_.
toString() <<
" cycle: " <<
oldCycle_ << std::endl;
128 std::cerr <<
"Original bus: " <<
oldBus_->
name() << std::endl;
131 for (
int i = 0; i < ins->
moveCount(); i++) {
136 std::cerr <<
"ins contains " << ins->
immediateCount() <<
" immediates." << std::endl;
145 #ifdef DEBUG_BUBBLEFISH_SCHEDULER
146 std::cerr <<
"BFUnscheudleMove undo" << std::endl;
virtual int immediateWriteCycle(const MoveNode &) const
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
virtual TCEString name() const
MoveNodeDuplicator & duplicator() const
std::string toString() const
const TTAMachine::Bus * oldBus_
virtual int index() const
bool isDestinationOperation() const
Terminal & destination() const
const TTAMachine::Bus & bus() const
const TTAMachine::FunctionUnit * dstFU_
ProgramOperation & sourceOperation() const
#define assert(condition)
virtual bool isImmediateRegister() const
SimpleResourceManager * prologRM() const
static int recurseCounter_
bool isSourceOperation() const
virtual const TTAMachine::ImmediateUnit & immediateUnit() const
DataDependenceGraph & ddg()
SimpleResourceManager & rm() const
const TTAMachine::ImmediateUnit * immu_
virtual void writeToDotFile(const TCEString &fileName) const
virtual const TTAMachine::FunctionUnit & functionUnit() const
MoveNode * getMoveNode(MoveNode &mn)
ProgramOperation & destinationOperation(unsigned int index=0) const
void unscheduleOriginal()
TTAProgram::Move & move()
std::string toString() const
static std::string disassemble(const TTAProgram::Move &move)
const TTAMachine::Bus * prologBus_
int immediateCount() const
Terminal & source() const
const TTAMachine::FunctionUnit * srcFU_
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
virtual TTAProgram::Instruction * instruction(int cycle) const override