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64 int lastRegisterIndex = rf.
size()-1;
78 for (
auto iEdge : iEdges) {
79 if (!iEdge->isRegisterOrRA() || iEdge->headPseudo()) {
84 if (iEdge->guardUse() &&
89 }
else if (iEdge->isRAW()) {
97 for (
auto oEdge : oEdges) {
98 if (!oEdge->isRegisterOrRA() || oEdge->tailPseudo()) {
102 !oEdge->guardUse()) {
121 tempRegName, bbn,
ii()!= 0);
Port * firstReadPort() const
void createAntidepsForReg(MoveNode &firstMove, MoveNode &lastMove, const TTAMachine::RegisterFile &rf, int index, TCEString regName, BasicBlockNode &bbn, bool loopScheduling)
virtual Node & tailNode(const Edge &edge) const
virtual TCEString name() const
virtual Node & headNode(const Edge &edge) const
std::set< const TTAMachine::RegisterFile *, TTAMachine::MachinePart::Comparator > possibleTempRegRFs(const MoveNode &mn, bool tempRegAfter, const TTAMachine::RegisterFile *forbiddenRF=nullptr)
const TTAMachine::RegisterFile * forbiddenRF_
static std::string toString(const T &source)
bool splitMove(BasicBlockNode &bbn)
void setDestination(Terminal *dst)
Port * firstWritePort() const
DataDependenceGraph & ddg()
virtual EdgeSet inEdges(const Node &node) const
virtual EdgeSet outEdges(const Node &node) const
TTAProgram::Move & move()
virtual Terminal * copy() const =0
Terminal & source() const
bool runPostChild(Reversible *preChild)
void setSource(Terminal *src)