64    int lastRegisterIndex = rf.
size()-1;
 
   78    for (
auto iEdge : iEdges) {
 
   79        if (!iEdge->isRegisterOrRA() || iEdge->headPseudo()) {
 
   84        if (iEdge->guardUse() &&
 
   89        } 
else if (iEdge->isRAW()) {
 
   97    for (
auto oEdge : oEdges) {
 
   98        if (!oEdge->isRegisterOrRA() || oEdge->tailPseudo()) {
 
  102            !oEdge->guardUse()) {
 
  121        tempRegName, bbn, 
ii()!= 0);
 
 
std::set< const TTAMachine::RegisterFile *, TTAMachine::MachinePart::Comparator > possibleTempRegRFs(const MoveNode &mn, bool tempRegAfter, const TTAMachine::RegisterFile *forbiddenRF=nullptr)
 
DataDependenceGraph & ddg()
 
const TTAMachine::RegisterFile * forbiddenRF_
 
bool splitMove(BasicBlockNode &bbn)
 
void createAntidepsForReg(MoveNode &firstMove, MoveNode &lastMove, const TTAMachine::RegisterFile &rf, int index, TCEString regName, BasicBlockNode &bbn, bool loopScheduling)
 
virtual Node & headNode(const Edge &edge) const
 
virtual EdgeSet outEdges(const Node &node) const
 
virtual Node & tailNode(const Edge &edge) const
 
virtual EdgeSet inEdges(const Node &node) const
 
static std::string toString(const T &source)
 
TTAProgram::Move & move()
 
bool runPostChild(Reversible *preChild)
 
virtual TCEString name() const
 
Port * firstReadPort() const
 
Port * firstWritePort() const
 
void setSource(Terminal *src)
 
Terminal & source() const
 
void setDestination(Terminal *dst)
 
virtual Terminal * copy() const =0