OpenASIP  2.0
HWGen/HDLPort.hh
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1 /*
2  Copyright (c) 2018 Tampere University.
3 
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24 /**
25  * @file Port.hh
26  *
27  * Port classes for HDLGenerator
28  *
29  * @author Aleksi Tervo 2018 (aleksi.tervo-no.spam-tut.fi)
30  */
31 
32 #include "HWGenTools.hh"
33 
34 namespace HDLGenerator {
35  /**
36  * Entity/module port base class.
37  */
38  class Port {
39  public:
40  Port(std::string name, Direction dir, int width = 1,
42  : name_(name), dir_(dir), width_(width), wireType_(wireType) {}
43  Port(std::string name, Direction dir, std::string parametricWidth,
45  : name_(name), dir_(dir), parametricWidth_(parametricWidth),
46  width_(-1), wireType_(wireType) {}
47 
48  virtual ~Port() = default;
49 
50  void declare(std::ostream& stream, Language lang, int level = 0) {
51  stream << StringTools::indent(level);
52  if (lang == Language::VHDL) {
53  stream << name_;
54  if (dir_ == Direction::In) {
55  stream << " : in ";
56  } else {
57  stream << " : out ";
58  }
59  if (!parametricWidth_.empty()) {
60  stream << "std_logic_vector(" << parametricWidth_
61  << "-1 downto 0)";
62  } else if (wireType_ == WireType::Vector || width_ > 1) {
63  stream << "std_logic_vector("
64  << std::to_string(width_) << "-1 downto 0)";
65  } else {
66  stream << "std_logic";
67  }
68  } else if (lang == Language::Verilog) {
69  if (dir_ == Direction::In) {
70  stream << "input ";
71  } else {
72  stream << "output reg ";
73  }
74  if (!parametricWidth_.empty()) {
75  stream << "[" << parametricWidth_ << "-1:0] ";
76  } else if (wireType_ == WireType::Vector || width_ > 1) {
77  stream << "[" << std::to_string(width_ - 1) << ":0] ";
78  }
79  stream << name_;
80  } else {
81  throw std::runtime_error(__PRETTY_FUNCTION__);
82  }
83  };
84 
85  std::string name() { return name_; }
86 
88 
89  WireType wireType() const { return wireType_; }
90 
91  protected:
92  std::string name_;
94  std::string parametricWidth_;
95  int width_;
97  };
98 
99  class OutPort : public Port {
100  public:
101  OutPort(std::string name, int width = 1,
103  : Port(name, Direction::Out, width, wireType) {}
104  OutPort(std::string name, std::string parametricWidth,
106  : Port(name, Direction::Out, parametricWidth, wireType) {}
107 
108  };
109 
110  class InPort : public Port {
111  public:
112  InPort(std::string name, int width = 1,
114  : Port(name, Direction::In, width, wireType) {}
115  InPort(std::string name, std::string parametricWidth,
117  : Port(name, Direction::In, parametricWidth, wireType) {}
118  };
119 }
HDLGenerator
Definition: BinaryOps.hh:35
StringTools::indent
static std::string indent(int level)
Definition: StringTools.cc:319
HDLGenerator::Port::dir_
Direction dir_
Definition: HWGen/HDLPort.hh:93
HDLGenerator::InPort::InPort
InPort(std::string name, std::string parametricWidth, WireType wireType=WireType::Auto)
Definition: HWGen/HDLPort.hh:115
HDLGenerator::Port::wireType
WireType wireType() const
Definition: HWGen/HDLPort.hh:89
HDLGenerator::Direction::In
@ In
HDLGenerator::OutPort::OutPort
OutPort(std::string name, int width=1, WireType wireType=WireType::Auto)
Definition: HWGen/HDLPort.hh:101
HDLGenerator::Port
Definition: HWGen/HDLPort.hh:38
HDLGenerator::Port::wireType_
WireType wireType_
Definition: HWGen/HDLPort.hh:96
HDLGenerator::Port::width_
int width_
Definition: HWGen/HDLPort.hh:95
HDLGenerator::Port::width
Width width()
Definition: HWGen/HDLPort.hh:87
HDLGenerator::OutPort
Definition: HWGen/HDLPort.hh:99
HDLGenerator::WireType
WireType
Definition: HWGenTools.hh:34
HDLGenerator::Port::~Port
virtual ~Port()=default
HDLGenerator::Language::Verilog
@ Verilog
HDLGenerator::Port::Port
Port(std::string name, Direction dir, int width=1, WireType wireType=WireType::Auto)
Definition: HWGen/HDLPort.hh:40
HDLGenerator::Language
Language
Definition: HWGenTools.hh:33
HDLGenerator::InPort::InPort
InPort(std::string name, int width=1, WireType wireType=WireType::Auto)
Definition: HWGen/HDLPort.hh:112
HDLGenerator::InPort
Definition: HWGen/HDLPort.hh:110
HWGenTools.hh
HDLGenerator::Direction::Out
@ Out
HDLGenerator::OutPort::OutPort
OutPort(std::string name, std::string parametricWidth, WireType wireType=WireType::Auto)
Definition: HWGen/HDLPort.hh:104
HDLGenerator::Port::Port
Port(std::string name, Direction dir, std::string parametricWidth, WireType wireType=WireType::Auto)
Definition: HWGen/HDLPort.hh:43
HDLGenerator::WireType::Auto
@ Auto
HDLGenerator::WireType::Vector
@ Vector
HDLGenerator::Port::name
std::string name()
Definition: HWGen/HDLPort.hh:85
HDLGenerator::Direction
Direction
Definition: HWGenTools.hh:35
HDLGenerator::Port::name_
std::string name_
Definition: HWGen/HDLPort.hh:92
HDLGenerator::Port::declare
void declare(std::ostream &stream, Language lang, int level=0)
Definition: HWGen/HDLPort.hh:50
HDLGenerator::Language::VHDL
@ VHDL
HDLGenerator::Width
Definition: HWGenTools.hh:37
HDLGenerator::Port::parametricWidth_
std::string parametricWidth_
Definition: HWGen/HDLPort.hh:94