ProGeTypes.hh

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/*
    Copyright (c) 2002-2009 Tampere University.
 
    This file is part of TTA-Based Codesign Environment (TCE).
 
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/**
 * @file ProGeTypes.hh
 *
 * Declaration of the data types used in ProGe.
 *
 * @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
 * @author Vinogradov Viacheslav(added Verilog generating) 2012 
 * @note rating: red
 */
 
#ifndef TTA_PROGE_TYPES_HH
#define TTA_PROGE_TYPES_HH
 
namespace ProGe {
 
/// HDLs supported by ProGe.
enum HDL {
    VHDL=0, ///< VHDL
    Verilog ///< Verilog
};
 
/// Data types of hardware ports.
enum DataType {
    BIT, ///< One bit.
    BIT_VECTOR ///< Several bits.
};
 
/// Direction of the port.
enum Direction {
    IN, ///< Input port.
    OUT, ///< Output port.
    BIDIR ///< Bidirectional port.
};
 
}
 
#endif