ProGe Namespace Reference

Classes
class	BaseNetlistBlock
class	BlockSourceCopier
class	CUOpcodeGenerator
class	GeneratableFUNetlistBlock
class	GlobalPackage
class	ICDecoderGeneratorPlugin
class	IGenerationPhases
class	InBitPort
	Convenience class for input bit ports. More...
class	InPort
	Convenience class for input ports. More...
class	InverterBlock
class	LoopBufferBlock
class	MemoryBusInterface
class	MicroCodeGenerator
class	Netlist
class	NetlistBlock
class	NetlistBlockNameComparator
class	NetlistGenerator
class	NetlistPort
class	NetlistPortGroup
class	NetlistTools
class	NetlistVisualization
class	NetlistWriter
class	OutBitPort
	Convenience class for output bit ports. More...
class	OutPort
	Convenience class for output ports. More...
class	Parameter
class	PortConnectionProperty
class	PortFactory
class	ProcessorGenerator
class	ProcessorWrapperBlock
class	ProGeContext
class	ProGeUI
class	RV32MicroCodeGenerator
class	Signal
class	SignalGroup
class	SinglePortByteMaskSSRAMBlock
class	SinglePortSSRAMBlock
class	StaticSignal
class	TestBenchBlock
class	VerilogNetlistWriter
class	VHDLNetlistWriter
class	VirtualNetlistBlock

Enumerations
enum	HDL { VHDL =0, Verilog }
	HDLs supported by ProGe. More...
enum	DataType { BIT, BIT_VECTOR }
	Data types of hardware ports. More...
enum	Direction { IN, OUT, BIDIR }
	Direction of the port. More...
enum	SignalGroupType {   SignalGroupType::UNDEFINED = 0, SignalGroupType::INTERNAL, SignalGroupType::USERDEFINED, SignalGroupType::INSTRUCTION_LINE,   SignalGroupType::BURST_INSTRUCTION, SignalGroupType::BITMASKED_SRAM_PORT, SignalGroupType::BITMASKED_ROM_PORT, SignalGroupType::BYTEMASKED_SRAM_PORT }
enum	SignalType {   SignalType::UNDEFINED = 0, SignalType::OPEN, SignalType::INTERNAL, SignalType::USERDEFINED,   SignalType::CLOCK, SignalType::RESET, SignalType::ADDRESS, SignalType::INSTRUCTIONWORD,   SignalType::FETCHBLOCK, SignalType::READ_REQUEST, SignalType::BURST_READ_REQUEST, SignalType::READ_REQUEST_READY,   SignalType::BURST_READ_REQUEST_READY, SignalType::WRITE_REQUEST, SignalType::READ_WRITE_REQUEST, SignalType::WRITEMODE,   SignalType::ENABLE, SignalType::BUSY, SignalType::STALL = BUSY, SignalType::GLOCK_REQUEST,   SignalType::GLOCK, SignalType::INVALIDATE_CACHE, SignalType::READ_DATA, SignalType::WRITE_DATA,   SignalType::WRITE_BITMASK, SignalType::CORE_HALT_STATUS, SignalType::AVALID, SignalType::AREADY,   SignalType::AADDR, SignalType::AWREN, SignalType::ASTRB, SignalType::RVALID,   SignalType::RREADY, SignalType::RDATA, SignalType::ADATA }
enum	ActiveState { ActiveState::HIGH = 0, ActiveState::LOW }

Functions
std::set< SignalType >	signalGroupDefinition (SignalGroupType type)

Enumeration Type Documentation

ActiveState

enum ProGe::ActiveState

strong

Enumerator
HIGH
LOW

Definition at line 118 of file SignalTypes.hh.

                       {
    HIGH = 0,
    LOW
};

DataType

enum ProGe::DataType

Data types of hardware ports.

Enumerator
BIT	One bit.
BIT_VECTOR	Several bits.

Definition at line 46 of file ProGeTypes.hh.

              {
    BIT, ///< One bit.
    BIT_VECTOR ///< Several bits.
};

Direction

enum ProGe::Direction

Direction of the port.

Enumerator
IN	Input port.
OUT	Output port.
BIDIR	Bidirectional port.

Definition at line 52 of file ProGeTypes.hh.

               {
    IN, ///< Input port.
    OUT, ///< Output port.
    BIDIR ///< Bidirectional port.
};

HDL

enum ProGe::HDL

HDLs supported by ProGe.

Enumerator
VHDL	VHDL.
Verilog	Verilog.

Definition at line 40 of file ProGeTypes.hh.

         {
    VHDL=0, ///< VHDL
    Verilog ///< Verilog
};

SignalGroupType

enum ProGe::SignalGroupType

strong

List of signal group types. See SignalGroupDefinition.hh for definitions of the group types.

Enumerator
UNDEFINED
INTERNAL	Signal group is internally defined custom signal.
USERDEFINED	Signal group is externally defined custom signal.
INSTRUCTION_LINE	Signal group type for serial TTA instruction bus.
BURST_INSTRUCTION	Signal group type for burst TTA instruction bus.
BITMASKED_SRAM_PORT	Signal group type for one port SRAM having read and write capability and bitmask for writing.
BITMASKED_ROM_PORT	Signal group type for one port ROM.
BYTEMASKED_SRAM_PORT	Signal group type for one port SRAM having read and write capability and bitmask for writing with separate address and data handshake.

Definition at line 43 of file SignalGroupTypes.hh.

                           {
    UNDEFINED = 0,
    /// Signal group is internally defined custom signal.
    INTERNAL,
    /// Signal group is externally defined custom signal.
    USERDEFINED,
    /// Signal group type for serial TTA instruction bus.
    INSTRUCTION_LINE,
    /// Signal group type for burst TTA instruction bus.
    BURST_INSTRUCTION,
    /// Signal group type for one port SRAM having read and write capability
    /// and bitmask for writing.
    BITMASKED_SRAM_PORT,
    /// Signal group type for one port ROM.
    BITMASKED_ROM_PORT,
    /// Signal group type for one port SRAM having read and write capability
    /// and bitmask for writing with separate address and data handshake.
    BYTEMASKED_SRAM_PORT
};

SignalType

enum ProGe::SignalType

strong

List of different types of signal. The types are also used as numerical IDs for connecting similiar NetlistPorts together.

Enumerator
UNDEFINED	Signal does not have specified usage.
OPEN	Signal is left to unconnected.
INTERNAL	Signal is internally defined custom signal.
USERDEFINED	Signal is externally defined custom signal.
CLOCK	Clock signal.
RESET	Reset signal.
ADDRESS	Signal holds address.
INSTRUCTIONWORD	Signal contains TTA (decompressed) instruction.
FETCHBLOCK	Signal is TTA instruction block block containing (compressed) instruction.
READ_REQUEST	Signal to make read request.
BURST_READ_REQUEST	Signal to make burst read request.
READ_REQUEST_READY	Signal to tell that requested data can be read.
BURST_READ_REQUEST_READY	Signal to tell that part of burst-requested data can be read.
WRITE_REQUEST	Signal to make write request.
READ_WRITE_REQUEST	Signal to make either read or write request.
WRITEMODE	Signal to choose mode for READ_WRITE_REQUEST or similar.
ENABLE	Signal to enable or activate a device.
BUSY	Signal telling that source device is not ready to handle a request.
STALL	Signal to stopping destination device.
GLOCK_REQUEST	TTA Global lock request signal.
GLOCK	TTA Global lock signal.
INVALIDATE_CACHE	Cache Invalidation signal.
READ_DATA
WRITE_DATA
WRITE_BITMASK
CORE_HALT_STATUS	Signal that tell if core is halted.
AVALID	Signal types for memory interface with separate valid/ready in address/data.
AREADY
AADDR
AWREN
ASTRB
RVALID
RREADY
RDATA
ADATA

Definition at line 42 of file SignalTypes.hh.

                      {
    /// Signal does not have specified usage.
    UNDEFINED = 0,
    /// Signal is left to unconnected.
    OPEN,
    /// Signal is internally defined custom signal.
    INTERNAL,
    /// Signal is externally defined custom signal.
    USERDEFINED,
    /// Clock signal.
    CLOCK,
    /// Reset signal.
    RESET,
    /// Signal holds address.
    ADDRESS,
    /// Signal contains TTA (decompressed) instruction.
    INSTRUCTIONWORD,
    /// Signal is TTA instruction block block containing (compressed)
    /// instruction.
    FETCHBLOCK,
    /// Signal to make read request.
    READ_REQUEST,
    /// Signal to make burst read request.
    BURST_READ_REQUEST,
    /// Signal to tell that requested data can be read.
    READ_REQUEST_READY,
    /// Signal to tell that part of burst-requested data can be read.
    BURST_READ_REQUEST_READY,
    /// Signal to make write request.
    WRITE_REQUEST,
    /// Signal to make either read or write request.
    READ_WRITE_REQUEST,
    /// Signal to choose mode for READ_WRITE_REQUEST or similar.
    WRITEMODE,
    /// Signal to enable or activate a device.
    ENABLE,
    /// Signal telling that source device is not ready to handle a request.
    BUSY,
    /// Signal to stopping destination device.
    STALL = BUSY,
    /// TTA Global lock request signal.
    GLOCK_REQUEST,
    /// TTA Global lock signal.
    GLOCK,
    /// Cache Invalidation signal.
    INVALIDATE_CACHE,
    READ_DATA,
    WRITE_DATA,
    WRITE_BITMASK,
    /// Signal that tell if core is halted.
    CORE_HALT_STATUS,
 
    /// Signal types for memory interface with separate
    /// valid/ready in address/data
    AVALID,
    AREADY,
    AADDR,
    AWREN,
    ASTRB,
    RVALID,
    RREADY,
    RDATA,
    ADATA
 
    //todo consider these:
    //DATA
    //DATA0..DATAn < for vectors, 0..n to point vector element
    //VECTORDATA < alternative for vector, SignalID to point vector element
    //INSTRUCTION_ADDRESS
    //DATA_ADDRESS
    //FU_OPCODE
    //FU_TRIGGER or FU_TRIGGER_LOAD = WRITE_REQUEST = LOAD
    //FU_DATA < Either for trigger, operand or result data. Determined by
    //          associated SignalGroupType
};

Function Documentation

signalGroupDefinition()

std::set< SignalType > ProGe::signalGroupDefinition

(

SignalGroupType

type

)

Returns set of SignalTypes defined by SignalGroupType.

Definition at line 86 of file SignalGroupDefinitions.cc.

                                            {
    if (definitions.count(type)) {
        return definitions.at(type);
    } else {
        return std::set<SignalType>();
    }
}