OpenASIP  2.0
ProGe::ProcessorWrapperBlock Member List

This is the complete list of members for ProGe::ProcessorWrapperBlock, including all inherited members.

addDataMemory(const MemoryBusInterface &)ProGe::ProcessorWrapperBlockprivate
addDataMemory2(const MemoryBusInterface &)ProGe::ProcessorWrapperBlockprivate
addInstructionMemory(const NetlistPortGroup &)ProGe::ProcessorWrapperBlockprivate
addPackage(const std::string &packageName)ProGe::BaseNetlistBlockprotected
addParameter(const Parameter &param)ProGe::BaseNetlistBlockprotected
addPort(NetlistPort *port)ProGe::BaseNetlistBlockprotected
addPortGroup(NetlistPortGroup *portGroup)ProGe::BaseNetlistBlockprotected
addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")ProGe::BaseNetlistBlockprotected
BaseNetlistBlock()ProGe::BaseNetlistBlock
BaseNetlistBlock(BaseNetlistBlock *parent)ProGe::BaseNetlistBlockexplicit
BaseNetlistBlock(const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)ProGe::BaseNetlistBlock
BaseNetlistBlock(const BaseNetlistBlock &)ProGe::BaseNetlistBlockprivate
BlockContainerType typedefProGe::BaseNetlistBlock
build() overrideProGe::BaseNetlistBlockvirtual
connect() overrideProGe::BaseNetlistBlockvirtual
connectClocks()ProGe::BaseNetlistBlockprotected
connectLockStatus(const NetlistPort &topPCInitPort)ProGe::ProcessorWrapperBlockprivate
connectPCInit(const NetlistPort &topPCInitPort)ProGe::ProcessorWrapperBlockprivate
connectResets()ProGe::BaseNetlistBlockprotected
context_ProGe::ProcessorWrapperBlockprivate
coreBlock_ProGe::ProcessorWrapperBlockprivate
deleteSubBlock(BaseNetlistBlock *subBlock)ProGe::BaseNetlistBlockprotected
finalize() overrideProGe::BaseNetlistBlockvirtual
findPort(const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) constProGe::BaseNetlistBlockprotected
handleUnconnectedPorts()ProGe::ProcessorWrapperBlockprivate
hasParameter(const std::string &name) constProGe::BaseNetlistBlockvirtual
hasParentBlock() constProGe::BaseNetlistBlockvirtual
hasPortsBy(SignalType type) constProGe::BaseNetlistBlockvirtual
hasSubBlock(const std::string &instanceName) constProGe::BaseNetlistBlockvirtual
imemCount_ProGe::ProcessorWrapperBlockprivate
instanceName() constProGe::BaseNetlistBlock
instanceName_ProGe::BaseNetlistBlockprivate
isLeaf() constProGe::BaseNetlistBlockinlinevirtual
isSubBlock(const BaseNetlistBlock &block) constProGe::BaseNetlistBlockvirtual
isVirtual() constProGe::BaseNetlistBlockinlinevirtual
moduleName() constProGe::BaseNetlistBlock
moduleName_ProGe::BaseNetlistBlockprivate
name() constProGe::BaseNetlistBlock
netlist() constProGe::BaseNetlistBlockvirtual
netlist()ProGe::BaseNetlistBlockprotected
netlist_ProGe::BaseNetlistBlockprivate
operator=(const BaseNetlistBlock &)ProGe::BaseNetlistBlockprivate
package(size_t idx) constProGe::BaseNetlistBlockvirtual
packageCount() constProGe::BaseNetlistBlockvirtual
packages_ProGe::BaseNetlistBlockprivate
parameter(const std::string &name) constProGe::BaseNetlistBlockvirtual
parameter(size_t index) constProGe::BaseNetlistBlockvirtual
parameter(const std::string &name)ProGe::BaseNetlistBlockprotected
ParameterContainerType typedefProGe::BaseNetlistBlock
parameterCount() constProGe::BaseNetlistBlockvirtual
parameters_ProGe::BaseNetlistBlockprivate
parent_ProGe::BaseNetlistBlockprivate
parentBlock() constProGe::BaseNetlistBlockvirtual
parentBlock()ProGe::BaseNetlistBlockprotectedvirtual
port(size_t index) constProGe::BaseNetlistBlockvirtual
port(const std::string &portName, bool partialMatch=true) constProGe::BaseNetlistBlockvirtual
port(size_t index)ProGe::BaseNetlistBlockprotectedvirtual
portBy(SignalType type, size_t index=0) constProGe::BaseNetlistBlockvirtual
PortContainerType typedefProGe::BaseNetlistBlock
portCount() constProGe::BaseNetlistBlockvirtual
portGroup(size_t index) constProGe::BaseNetlistBlockvirtual
PortGroupContainerType typedefProGe::BaseNetlistBlock
portGroupCount() constProGe::BaseNetlistBlockvirtual
portGroups_ProGe::BaseNetlistBlockprivate
portGroupsBy(SignalGroupType type) constProGe::BaseNetlistBlockvirtual
ports()ProGe::BaseNetlistBlockinline
ports_ProGe::BaseNetlistBlockprivate
portsBy(SignalType type) constProGe::BaseNetlistBlockvirtual
ProcessorWrapperBlock()=deleteProGe::ProcessorWrapperBlock
ProcessorWrapperBlock(const ProGeContext &context, const BaseNetlistBlock &processorBlock)ProGe::ProcessorWrapperBlock
removePort(NetlistPort *port)ProGe::BaseNetlistBlockprotected
removePortGroup(NetlistPortGroup *portGroup)ProGe::BaseNetlistBlockprotected
removeSubBlock(BaseNetlistBlock *subBlock)ProGe::BaseNetlistBlockprotected
setInstanceName(const std::string &name)ProGe::BaseNetlistBlock
setModuleName(const std::string &name)ProGe::BaseNetlistBlockprotected
setParameter(const Parameter &param)ProGe::BaseNetlistBlockprotected
setParent(BaseNetlistBlock *parent)ProGe::BaseNetlistBlockprivatevirtual
shallowCopy(const std::string &instanceName="") constProGe::BaseNetlistBlock
subBlock(size_t index) constProGe::BaseNetlistBlockvirtual
subBlock(size_t index)ProGe::BaseNetlistBlockprotectedvirtual
subBlockCount() constProGe::BaseNetlistBlockvirtual
subBlocks_ProGe::BaseNetlistBlockprivate
write(const Path &targetBaseDir, HDL targetLang=VHDL) const overrideProGe::ProcessorWrapperBlockvirtual
writeSelf(const Path &targetBaseDir, HDL targetLang=VHDL) constProGe::BaseNetlistBlockvirtual
~BaseNetlistBlock()ProGe::BaseNetlistBlockvirtual
~IGenerationPhases()ProGe::IGenerationPhasesinlinevirtual
~ProcessorWrapperBlock()ProGe::ProcessorWrapperBlockvirtual
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