OpenASIP
2.0
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#include <BaseNetlistBlock.hh>
Public Types | |
typedef std::vector< BaseNetlistBlock * > | BlockContainerType |
typedef std::vector< Parameter > | ParameterContainerType |
typedef std::vector< NetlistPort * > | PortContainerType |
typedef std::vector< NetlistPortGroup * > | PortGroupContainerType |
Public Member Functions | |
BaseNetlistBlock () | |
BaseNetlistBlock (BaseNetlistBlock *parent) | |
BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr) | |
virtual | ~BaseNetlistBlock () |
const std::string & | instanceName () const |
void | setInstanceName (const std::string &name) |
const std::string & | moduleName () const |
const std::string | name () const |
virtual size_t | subBlockCount () const |
virtual const BaseNetlistBlock & | subBlock (size_t index) const |
virtual bool | hasSubBlock (const std::string &instanceName) const |
virtual bool | isSubBlock (const BaseNetlistBlock &block) const |
virtual bool | hasParameter (const std::string &name) const |
virtual const Parameter & | parameter (const std::string &name) const |
virtual size_t | parameterCount () const |
virtual const Parameter & | parameter (size_t index) const |
virtual size_t | portCount () const |
virtual const NetlistPort & | port (size_t index) const |
virtual std::vector< const NetlistPort * > | portsBy (SignalType type) const |
virtual const NetlistPort & | portBy (SignalType type, size_t index=0) const |
virtual bool | hasPortsBy (SignalType type) const |
virtual const NetlistPort * | port (const std::string &portName, bool partialMatch=true) const |
virtual size_t | portGroupCount () const |
virtual const NetlistPortGroup & | portGroup (size_t index) const |
virtual std::vector< const NetlistPortGroup * > | portGroupsBy (SignalGroupType type) const |
virtual const Netlist & | netlist () const |
virtual bool | hasParentBlock () const |
virtual const BaseNetlistBlock & | parentBlock () const |
virtual bool | isVirtual () const |
virtual void | build () override |
virtual void | connect () override |
virtual void | finalize () override |
virtual void | write (const Path &targetBaseDir, HDL targetLang=VHDL) const override |
virtual void | writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const |
virtual size_t | packageCount () const |
virtual const std::string & | package (size_t idx) const |
PortContainerType & | ports () |
virtual bool | isLeaf () const |
BaseNetlistBlock * | shallowCopy (const std::string &instanceName="") const |
Public Member Functions inherited from ProGe::IGenerationPhases | |
virtual | ~IGenerationPhases () |
Protected Member Functions | |
Netlist & | netlist () |
virtual NetlistPort & | port (size_t index) |
virtual BaseNetlistBlock & | subBlock (size_t index) |
virtual BaseNetlistBlock & | parentBlock () |
void | setModuleName (const std::string &name) |
void | addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="") |
void | deleteSubBlock (BaseNetlistBlock *subBlock) |
void | removeSubBlock (BaseNetlistBlock *subBlock) |
NetlistPort * | addPort (NetlistPort *port) |
void | removePort (NetlistPort *port) |
void | addPortGroup (NetlistPortGroup *portGroup) |
void | removePortGroup (NetlistPortGroup *portGroup) |
void | setParameter (const Parameter ¶m) |
void | addParameter (const Parameter ¶m) |
Parameter & | parameter (const std::string &name) |
NetlistPort * | findPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const |
void | addPackage (const std::string &packageName) |
void | connectClocks () |
void | connectResets () |
Private Member Functions | |
BaseNetlistBlock (const BaseNetlistBlock &) | |
BaseNetlistBlock & | operator= (const BaseNetlistBlock &) |
virtual void | setParent (BaseNetlistBlock *parent) |
Private Attributes | |
BaseNetlistBlock * | parent_ |
The reference to parent block of this block. More... | |
BlockContainerType | subBlocks_ |
The sub blocks of this netlist block. More... | |
ParameterContainerType | parameters_ |
The parameters of the block. More... | |
PortContainerType | ports_ |
The ports of the block. More... | |
PortGroupContainerType | portGroups_ |
The ports of the block. More... | |
Netlist * | netlist_ |
The netlist of the block. More... | |
std::string | instanceName_ |
The instance name of the block. More... | |
std::string | moduleName_ |
The module name of the block. More... | |
std::vector< std::string > | packages_ |
The referenced packages by the module. More... | |
Friends | |
class | NetlistPort |
class | NetlistPortGroup |
class | Parameter |
Definition at line 59 of file BaseNetlistBlock.hh.
typedef std::vector<BaseNetlistBlock*> ProGe::BaseNetlistBlock::BlockContainerType |
Definition at line 65 of file BaseNetlistBlock.hh.
typedef std::vector<Parameter> ProGe::BaseNetlistBlock::ParameterContainerType |
Definition at line 66 of file BaseNetlistBlock.hh.
typedef std::vector<NetlistPort*> ProGe::BaseNetlistBlock::PortContainerType |
Definition at line 67 of file BaseNetlistBlock.hh.
typedef std::vector<NetlistPortGroup*> ProGe::BaseNetlistBlock::PortGroupContainerType |
Definition at line 68 of file BaseNetlistBlock.hh.
ProGe::BaseNetlistBlock::BaseNetlistBlock | ( | ) |
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explicit |
Definition at line 64 of file BaseNetlistBlock.cc.
References addSubBlock(), and parent_.
ProGe::BaseNetlistBlock::BaseNetlistBlock | ( | const std::string & | moduleName, |
const std::string & | instanceName, | ||
BaseNetlistBlock * | parent = nullptr |
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Definition at line 79 of file BaseNetlistBlock.cc.
References addSubBlock(), instanceName(), moduleName(), parent_, and setInstanceName().
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Definition at line 100 of file BaseNetlistBlock.cc.
References netlist_, parent_, portGroups_, ports_, removeSubBlock(), and subBlocks_.
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private |
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Definition at line 687 of file BaseNetlistBlock.cc.
References ContainerTools::containsValue(), and packages_.
Referenced by addParameter(), ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), and shallowCopy().
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Adds new parameter to the block. Throws exception if the block has the parameter by the name already.
Definition at line 547 of file BaseNetlistBlock.cc.
References addPackage(), assert, name(), ProGe::Parameter::name(), ProGe::Parameter::packageNameOfConstant(), parameters_, and ProGe::Parameter::valueIsConstant().
Referenced by ProGe::LoopBufferBlock::LoopBufferBlock(), ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().
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Adds port to this block and acquires ownership of it.
Added port will point to this block after the call.
ObjectAlreadyExists | Thrown if the netlist block already has a port by same name. |
Definition at line 467 of file BaseNetlistBlock.cc.
References assert, findPort(), ProGe::NetlistPort::hasParentBlock(), ProGe::NetlistPort::name(), netlist_, parent_, ProGe::NetlistPort::parentBlock(), port(), ports_, ProGe::Netlist::registerPort(), ProGe::NetlistPort::setParent(), and THROW_EXCEPTION.
Referenced by addPortGroup(), ProGe::LoopBufferBlock::LoopBufferBlock(), ProGe::NetlistPort::NetlistPort(), ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().
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Definition at line 508 of file BaseNetlistBlock.cc.
References addPort(), netlist(), ProGe::NetlistPortGroup::portAt(), ProGe::NetlistPortGroup::portCount(), portGroup(), portGroups_, and ProGe::NetlistPortGroup::setParent().
Referenced by shallowCopy(), ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().
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Adds sub block to this block and acquires ownership of it.
subBlock | The block to be added. |
instanceName | The instance base name to be given for sub block. If the given or sub block's instance name is not unique within the block The name will be prefixed with a running number. |
Definition at line 405 of file BaseNetlistBlock.cc.
References assert, ProGe::NetlistTools::getUniqueInstanceName(), hasParentBlock(), instanceName(), instanceName_, moduleName(), netlist_, parentBlock(), port(), portCount(), ProGe::Netlist::registerPort(), setInstanceName(), setParent(), subBlock(), and subBlocks_.
Referenced by ProGe::ProcessorWrapperBlock::addInstructionMemory(), BaseNetlistBlock(), and ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock().
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overridevirtual |
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overridevirtual |
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Connects all unconnected clock ports of sub block to this block's clock port if there is one.
Definition at line 722 of file BaseNetlistBlock.cc.
References assert, ProGe::CLOCK, ProGe::Netlist::connect(), ProGe::NetlistPort::direction(), netlist(), port(), portsBy(), subBlock(), and subBlockCount().
Referenced by ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock().
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Connects all unconnected reset ports of sub block to this block's reset port if there is one.
Definition at line 743 of file BaseNetlistBlock.cc.
References assert, ProGe::Netlist::connect(), ProGe::NetlistPort::direction(), netlist(), port(), portsBy(), ProGe::RESET, subBlock(), and subBlockCount().
Referenced by ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock().
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Deletes given sub block and its all sub blocks.
Definition at line 434 of file BaseNetlistBlock.cc.
References subBlock(), subBlocks_, and ContainerTools::swapRemoveValue().
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Returns a port that matches (partially) the given name.
If not found, returns nullptr
Definition at line 574 of file BaseNetlistBlock.cc.
References assert, portCount(), and ports_.
Referenced by addPort(), ProGe::NetlistBlock::port(), and port().
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virtual |
Definition at line 183 of file BaseNetlistBlock.cc.
References name(), ProGe::Parameter::name(), parameter(), and parameterCount().
Referenced by AlteraMemGenerator::addGenerics(), ProGe::LoopBufferBlock::setIterationPortWidthParameter(), and ProGe::VHDLNetlistWriter::usesParameterWidth().
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Definition at line 353 of file BaseNetlistBlock.cc.
References parent_.
Referenced by DefaultDecoderGenerator::addGlockPortToDecoder(), addSubBlock(), ProGe::NetlistTools::parent(), ProGe::NetlistBlock::parentBlock(), parentBlock(), removePort(), and setInstanceName().
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Return true if the netlist block has at least one port by given Signal Type.
Definition at line 300 of file BaseNetlistBlock.cc.
References ProGe::NetlistPort::assignedSignal(), port(), portCount(), and ProGe::Signal::type().
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Definition at line 160 of file BaseNetlistBlock.cc.
References instanceName(), subBlock(), and subBlockCount().
Referenced by ProGe::NetlistTools::getUniqueInstanceName(), and setInstanceName().
const std::string & ProGe::BaseNetlistBlock::instanceName | ( | ) | const |
Definition at line 135 of file BaseNetlistBlock.cc.
References instanceName_.
Referenced by ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), addSubBlock(), BaseNetlistBlock(), ProGe::NetlistGenerator::clkPort(), ProGe::NetlistGenerator::fuGuardPort(), ProGe::NetlistGenerator::fuOpcodePort(), DefaultICDecoderGenerator::generateDebuggerCode(), ProGe::NetlistGenerator::glockPort(), ProGe::NetlistGenerator::glockReqPort(), hasSubBlock(), ProGe::NetlistVisualization::listConnections(), ProGe::NetlistVisualization::listNetlistDescriptors(), ProGe::NetlistGenerator::loadPort(), ProGe::NetlistBlockNameComparator::operator()(), parameter(), ProGe::VHDLNetlistWriter::portSignalName(), ProGe::VerilogNetlistWriter::portSignalName(), ProGe::NetlistVisualization::printBlock(), ProGe::NetlistGenerator::rfGuardPort(), ProGe::NetlistGenerator::rfOpcodePort(), ProGe::NetlistGenerator::rstPort(), setInstanceName(), shallowCopy(), ProGe::VerilogNetlistWriter::writePortMappings(), and ProGe::VHDLNetlistWriter::writePortMappings().
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Returns true if the netlist block in the block hierarchy is a leaf block.
Leaf block are not modifiable: No ports, sub blocks or ports may be added or removed.
Definition at line 134 of file BaseNetlistBlock.hh.
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Returns true if the given netlist block is sub block of this block.
Definition at line 173 of file BaseNetlistBlock.cc.
References ContainerTools::containsValue(), and subBlocks_.
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inlinevirtual |
Reimplemented in ProGe::VirtualNetlistBlock.
Definition at line 112 of file BaseNetlistBlock.hh.
Referenced by ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writeSignalDeclarations(), and ProGe::VerilogNetlistWriter::writeSignalDeclarations().
const std::string & ProGe::BaseNetlistBlock::moduleName | ( | ) | const |
Definition at line 140 of file BaseNetlistBlock.cc.
References moduleName_.
Referenced by DefaultICGenerator::addICToNetlist(), addSubBlock(), BaseNetlistBlock(), ProGe::NetlistGenerator::clkPort(), DefaultDecoderGenerator::completeDecoderBlock(), FUGen::FUGen(), ProGe::NetlistGenerator::fuGuardPort(), ProGe::NetlistGenerator::fuOpcodePort(), DefaultICDecoderGenerator::generateDebuggerCode(), ProGe::NetlistGenerator::glockPort(), ProGe::NetlistGenerator::glockReqPort(), ProGe::NetlistGenerator::loadPort(), name(), ProGe::VerilogNetlistWriter::netlistParameterPkgName(), ProGe::VHDLNetlistWriter::netlistParameterPkgName(), ProGe::NetlistBlockNameComparator::operator()(), parameter(), ProGe::NetlistVisualization::printBlock(), ProGe::NetlistGenerator::rfGuardPort(), ProGe::NetlistGenerator::rfOpcodePort(), ProGe::NetlistGenerator::rstPort(), setInstanceName(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::TestBenchBlock::write(), ProGe::LoopBufferBlock::write(), ProGe::VHDLNetlistWriter::writeBlock(), ProGe::VerilogNetlistWriter::writeBlock(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writePortMappings(), and ProGe::VHDLNetlistWriter::writePortMappings().
const std::string ProGe::BaseNetlistBlock::name | ( | ) | const |
Definition at line 145 of file BaseNetlistBlock.cc.
References instanceName_, and moduleName().
Referenced by addParameter(), hasParameter(), parameter(), setInstanceName(), setModuleName(), and ProGe::NetlistBlock::setParameter().
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Definition at line 348 of file BaseNetlistBlock.cc.
References netlist_.
Referenced by ProGe::ProcessorWrapperBlock::addInstructionMemory(), addPortGroup(), connectClocks(), connectResets(), ProGe::NetlistVisualization::listConnections(), ProGe::NetlistVisualization::listNetlistDescriptors(), removePort(), ProGe::NetlistPort::resolveRealWidth(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::VerilogNetlistWriter::write(), ProGe::NetlistBlock::write(), ProGe::VHDLNetlistWriter::writeBlock(), ProGe::VerilogNetlistWriter::writeBlock(), ProGe::VHDLNetlistWriter::writeConnection(), ProGe::VHDLNetlistWriter::writeNetlistParameterPackage(), ProGe::VerilogNetlistWriter::writeNetlistParameterPackage(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalAssignments(), ProGe::VHDLNetlistWriter::writeSignalDeclarations(), and ProGe::VerilogNetlistWriter::writeSignalDeclarations().
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Definition at line 699 of file BaseNetlistBlock.cc.
References packages_.
Referenced by ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::VHDLNetlistWriter::writeBlock(), and ProGe::VerilogNetlistWriter::writeBlock().
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Definition at line 694 of file BaseNetlistBlock.cc.
References packages_.
Referenced by ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::VHDLNetlistWriter::writeBlock(), and ProGe::VerilogNetlistWriter::writeBlock().
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Returns a Parameter object by name.
NotAvailable | Thrown if the block does not have such Parameter. |
Definition at line 217 of file BaseNetlistBlock.cc.
References __func__, instanceName(), moduleName(), name(), parameterCount(), and parameters_.
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Returns a Parameter object by name.
NotAvailable | Thrown if the block does not have such Parameter. |
Definition at line 198 of file BaseNetlistBlock.cc.
References __func__, instanceName(), moduleName(), name(), ProGe::Parameter::name(), and parameterCount().
Referenced by hasParameter(), ProGe::VHDLNetlistWriter::parameterWidthValue(), ProGe::NetlistVisualization::printBlockTree(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writeGenericDeclaration(), ProGe::VHDLNetlistWriter::writeGenericDeclaration(), ProGe::VerilogNetlistWriter::writePortMappings(), and ProGe::VHDLNetlistWriter::writePortMappings().
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Definition at line 236 of file BaseNetlistBlock.cc.
References __func__, parameterCount(), and parameters_.
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Definition at line 231 of file BaseNetlistBlock.cc.
References parameters_.
Referenced by PlatformIntegrator::copyProgeBlockToNetlist(), hasParameter(), parameter(), ProGe::NetlistVisualization::printBlockTree(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writeGenericDeclaration(), ProGe::VHDLNetlistWriter::writeGenericDeclaration(), SOPCBuilderFileGenerator::writeGenerics(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), and IPXactFileGenerator::writeProjectFiles().
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Reimplemented in ProGe::NetlistBlock.
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Reimplemented in ProGe::NetlistBlock.
Definition at line 358 of file BaseNetlistBlock.cc.
References assert, hasParentBlock(), and parent_.
Referenced by addSubBlock(), ProGe::NetlistTools::parent(), ProGe::NetlistBlock::parentBlock(), removePort(), and setInstanceName().
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Returns a port that matches (partially) the given name.
Definition at line 317 of file BaseNetlistBlock.cc.
References findPort().
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Definition at line 322 of file BaseNetlistBlock.cc.
References ports_.
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Definition at line 253 of file BaseNetlistBlock.cc.
References ports_.
Referenced by addPort(), addSubBlock(), connectClocks(), connectResets(), hasPortsBy(), portsBy(), ProGe::NetlistVisualization::printBlockTree(), removePort(), removePortGroup(), ProGe::NetlistPort::rename(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VHDLNetlistWriter::writePortDeclaration(), ProGe::VerilogNetlistWriter::writePortDeclaration(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VerilogNetlistWriter::writeSignalAssignments(), ProGe::VHDLNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalDeclarations(), and ProGe::VHDLNetlistWriter::writeSignalDeclarations().
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Returns a port by Signal Type at given index.
The | list of ports by matching signal type at the index. |
OutOfRange | If the index is the number of found matches or larger. |
Definition at line 284 of file BaseNetlistBlock.cc.
References portsBy(), THROW_EXCEPTION, and Conversion::toString().
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Return port count in this block including ports from netlist port groups.
Definition at line 248 of file BaseNetlistBlock.cc.
References ports_.
Referenced by addSubBlock(), findPort(), hasPortsBy(), portsBy(), ProGe::NetlistVisualization::printBlockTree(), ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), ProGe::NetlistBlock::shallowCopy(), shallowCopy(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writePortDeclaration(), ProGe::VHDLNetlistWriter::writePortDeclaration(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VerilogNetlistWriter::writeSignalAssignments(), ProGe::VHDLNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalDeclarations(), and ProGe::VHDLNetlistWriter::writeSignalDeclarations().
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Definition at line 332 of file BaseNetlistBlock.cc.
References portGroups_.
Referenced by addPortGroup(), portGroupsBy(), ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), ProGe::NetlistBlock::shallowCopy(), and shallowCopy().
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Definition at line 327 of file BaseNetlistBlock.cc.
References portGroups_.
Referenced by portGroupsBy(), ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), ProGe::NetlistBlock::shallowCopy(), and shallowCopy().
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Definition at line 337 of file BaseNetlistBlock.cc.
References ProGe::NetlistPortGroup::assignedSignalGroup(), portGroup(), and portGroupCount().
Referenced by ProGe::ProcessorGenerator::instructionBus().
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Returns list of ports by Signal Type.
The | list of ports by matching signal type in insertion order. |
Definition at line 264 of file BaseNetlistBlock.cc.
References ProGe::NetlistPort::assignedSignal(), port(), portCount(), and ProGe::Signal::type().
Referenced by ProGe::Netlist::connectClocks(), connectClocks(), ProGe::Netlist::connectResets(), connectResets(), and portBy().
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Removes the given port from the block.
After call the port is parent block reference is set to nullptr.
Definition at line 494 of file BaseNetlistBlock.cc.
References assert, hasParentBlock(), netlist(), parentBlock(), ProGe::NetlistPort::parentBlock(), port(), ports_, ContainerTools::removeValueIfExists(), ProGe::NetlistPort::setParent(), and ProGe::Netlist::unregisterPort().
Referenced by ProGe::NetlistPort::~NetlistPort().
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Definition at line 519 of file BaseNetlistBlock.cc.
References port(), portGroups_, and ContainerTools::swapRemoveValue().
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Removes sub block from this block and does not delete it.
Definition at line 449 of file BaseNetlistBlock.cc.
References subBlock(), subBlocks_, and ContainerTools::swapRemoveValue().
Referenced by setParent(), and ~BaseNetlistBlock().
void ProGe::BaseNetlistBlock::setInstanceName | ( | const std::string & | name | ) |
Replaces the instance name of the block.
The new name must be unique within sub blocks of parent block it is attached to.
ObjectAlreadyExists | Thrown if the name is not unique. |
Definition at line 379 of file BaseNetlistBlock.cc.
References hasParentBlock(), hasSubBlock(), instanceName(), instanceName_, moduleName(), name(), parentBlock(), and THROW_EXCEPTION.
Referenced by addSubBlock(), and BaseNetlistBlock().
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Definition at line 392 of file BaseNetlistBlock.cc.
References moduleName_, and name().
Referenced by ProGe::LoopBufferBlock::LoopBufferBlock().
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Adds parameter to the block overwriting the existing one by name.
Definition at line 532 of file BaseNetlistBlock.cc.
References ProGe::Parameter::name(), and parameters_.
Referenced by ProGe::LoopBufferBlock::LoopBufferBlock(), ProGe::SinglePortByteMaskSSRAMBlock::setAccessTraceFile(), ProGe::SinglePortSSRAMBlock::setAccessTraceFile(), ProGe::LoopBufferBlock::setBlockWidthParameter(), ProGe::LoopBufferBlock::setBufferSizeParameter(), ProGe::LoopBufferBlock::setCoreIdParameter(), ProGe::LoopBufferBlock::setIterationPortWidthParameter(), ProGe::LoopBufferBlock::setUsageTracingParameter(), and shallowCopy().
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Changes parent block to given one.
Definition at line 707 of file BaseNetlistBlock.cc.
References parent_, and removeSubBlock().
Referenced by addSubBlock().
BaseNetlistBlock * ProGe::BaseNetlistBlock::shallowCopy | ( | const std::string & | instanceName = "" | ) | const |
Creates new netlist block that only includes without of its subblocks or interconnections.
Definition at line 640 of file BaseNetlistBlock.cc.
References addPackage(), ProGe::NetlistPortGroup::addPort(), addPortGroup(), assert, BaseNetlistBlock(), ProGe::NetlistPortGroup::clear(), ProGe::NetlistPortGroup::clone(), ProGe::NetlistPort::copyTo(), instanceName(), moduleName(), ProGe::NetlistPort::name(), netlist(), package(), packageCount(), parameter(), ProGe::Netlist::parameter(), parameterCount(), ProGe::Netlist::parameterCount(), port(), portCount(), portGroup(), portGroupCount(), ProGe::Netlist::setParameter(), and setParameter().
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Reimplemented in ProGe::NetlistBlock.
Definition at line 178 of file BaseNetlistBlock.cc.
References subBlocks_.
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Definition at line 155 of file BaseNetlistBlock.cc.
References subBlocks_.
Referenced by addSubBlock(), ProGe::Netlist::connectClocks(), connectClocks(), ProGe::Netlist::connectResets(), connectResets(), deleteSubBlock(), hasSubBlock(), ProGe::NetlistVisualization::printBlockTree(), removeSubBlock(), ProGe::NetlistBlock::subBlock(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalDeclarations(), and ProGe::VHDLNetlistWriter::writeSignalDeclarations().
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Definition at line 150 of file BaseNetlistBlock.cc.
References subBlocks_.
Referenced by connectClocks(), connectResets(), hasSubBlock(), ProGe::NetlistVisualization::printBlockTree(), ProGe::NetlistBlock::subBlock(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VerilogNetlistWriter::writeSignalAssignments(), ProGe::VHDLNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalDeclarations(), and ProGe::VHDLNetlistWriter::writeSignalDeclarations().
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Does nothing on self but calls write function on each sub block.
Implements ProGe::IGenerationPhases.
Reimplemented in ProGe::NetlistBlock, ProGe::LoopBufferBlock, ProGe::ProcessorWrapperBlock, ProGe::SinglePortByteMaskSSRAMBlock, ProGe::SinglePortSSRAMBlock, and ProGe::TestBenchBlock.
Definition at line 614 of file BaseNetlistBlock.cc.
References subBlocks_.
Referenced by ProGe::ProcessorWrapperBlock::write(), and ProGe::NetlistBlock::write().
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Writes HDL source of itself only using default netlist writer.
Definition at line 625 of file BaseNetlistBlock.cc.
References THROW_EXCEPTION, ProGe::Verilog, ProGe::VHDL, ProGe::VerilogNetlistWriter::write(), and ProGe::VHDLNetlistWriter::write().
Referenced by ProGe::ProcessorWrapperBlock::write().
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Definition at line 61 of file BaseNetlistBlock.hh.
Referenced by ProGe::GeneratableFUNetlistBlock::addInOperand(), and ProGe::GeneratableFUNetlistBlock::addOutOperand().
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Definition at line 62 of file BaseNetlistBlock.hh.
Referenced by ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().
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Definition at line 63 of file BaseNetlistBlock.hh.
Referenced by ProGe::LoopBufferBlock::LoopBufferBlock(), ProGe::SinglePortByteMaskSSRAMBlock::setAccessTraceFile(), ProGe::SinglePortSSRAMBlock::setAccessTraceFile(), ProGe::LoopBufferBlock::setBlockWidthParameter(), ProGe::LoopBufferBlock::setBufferSizeParameter(), ProGe::LoopBufferBlock::setCoreIdParameter(), ProGe::LoopBufferBlock::setIterationPortWidthParameter(), ProGe::NetlistBlock::setParameter(), ProGe::LoopBufferBlock::setUsageTracingParameter(), ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().
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The instance name of the block.
Definition at line 186 of file BaseNetlistBlock.hh.
Referenced by addSubBlock(), instanceName(), name(), and setInstanceName().
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The module name of the block.
Definition at line 188 of file BaseNetlistBlock.hh.
Referenced by moduleName(), and setModuleName().
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The netlist of the block.
Definition at line 184 of file BaseNetlistBlock.hh.
Referenced by addPort(), addSubBlock(), netlist(), and ~BaseNetlistBlock().
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The referenced packages by the module.
Definition at line 190 of file BaseNetlistBlock.hh.
Referenced by addPackage(), package(), and packageCount().
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The parameters of the block.
Definition at line 178 of file BaseNetlistBlock.hh.
Referenced by addParameter(), parameter(), parameterCount(), and setParameter().
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The reference to parent block of this block.
Definition at line 174 of file BaseNetlistBlock.hh.
Referenced by addPort(), BaseNetlistBlock(), hasParentBlock(), parentBlock(), setParent(), and ~BaseNetlistBlock().
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The ports of the block.
Definition at line 182 of file BaseNetlistBlock.hh.
Referenced by addPortGroup(), portGroup(), portGroupCount(), removePortGroup(), and ~BaseNetlistBlock().
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The ports of the block.
Definition at line 180 of file BaseNetlistBlock.hh.
Referenced by addPort(), findPort(), port(), portCount(), ports(), removePort(), and ~BaseNetlistBlock().
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The sub blocks of this netlist block.
Definition at line 176 of file BaseNetlistBlock.hh.
Referenced by addSubBlock(), deleteSubBlock(), isSubBlock(), removeSubBlock(), subBlock(), subBlockCount(), write(), and ~BaseNetlistBlock().