XilinxBlockRamGenerator Member List

This is the complete list of members for XilinxBlockRamGenerator, including all inherited members.

addLsu(TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)	MemoryGenerator
addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)	XilinxBlockRamGenerator	virtual
addParameter(const ProGe::Parameter &add)	MemoryGenerator	protected
addPort(const TCEString &name, HDLPort *port)	MemoryGenerator	protected
addPorts(std::string prefix, int addrWidth, int dataWidth)	XilinxBlockRamGenerator	protected
addrWidth_	MemoryGenerator	private
almaifBlock_	XilinxBlockRamGenerator	protected
almaifPortName(const TCEString &portBaseName)	XilinxBlockRamGenerator	protected
BlockPair typedef	MemoryGenerator	protected
checkFuPort(const std::string fuPort, std::vector< TCEString > &reasons) const	MemoryGenerator	protectedvirtual
CLOCK_PORT	MemoryGenerator	privatestatic
connectPorts(ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)	MemoryGenerator	protectedvirtual
connectToArbiter_	XilinxBlockRamGenerator	protected
corePortName(const TCEString &portBaseName, int coreId) const	MemoryGenerator	protected
createMemoryNetlistBlock(ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)	MemoryGenerator	protectedvirtual
DP_FILE	XilinxBlockRamGenerator	privatestatic
errorStream()	MemoryGenerator	protected
errorStream_	MemoryGenerator	private
generateComponentFile(TCEString outputPath)	XilinxBlockRamGenerator	virtual
generatesComponentHdlFile() const	XilinxBlockRamGenerator	virtual
hasLSUArchitecture() const	MemoryGenerator	protected
initFile_	MemoryGenerator	private
initializationFile() const	MemoryGenerator
instanceName(int coreId, int) const	XilinxBlockRamGenerator	protectedvirtual
instantiateTemplate(const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const	MemoryGenerator	protected
integrator_	MemoryGenerator	private
isCompatible(const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const	XilinxBlockRamGenerator	virtual
lsuArch_	MemoryGenerator	private
lsuArchitecture() const	MemoryGenerator	protected
lsuPorts_	MemoryGenerator	private
mauWidth_	MemoryGenerator	private
memoryAddrWidth() const	MemoryGenerator
MemoryGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)	MemoryGenerator
memoryIndexString(int coreId, int memIndex) const	MemoryGenerator	protected
memoryMauSize() const	MemoryGenerator
memoryTotalWidth() const	MemoryGenerator
memoryWidthInMaus() const	MemoryGenerator
memPorts_	MemoryGenerator	private
moduleName() const	XilinxBlockRamGenerator	protectedvirtual
overrideAddrWidth_	XilinxBlockRamGenerator	protected
parameter(int index) const	MemoryGenerator	protected
parameterCount() const	MemoryGenerator	protected
ParameterList typedef	MemoryGenerator	private
params_	MemoryGenerator	private
platformIntegrator() const	MemoryGenerator	protected
port(int index) const	MemoryGenerator	protected
portByKeyName(TCEString name) const	MemoryGenerator	protected
portCount() const	MemoryGenerator	protected
portKeyName(const HDLPort *port) const	MemoryGenerator	protected
PortMap typedef	MemoryGenerator	protected
RESET_PORT	MemoryGenerator	privatestatic
signalPrefix_	XilinxBlockRamGenerator	protected
singleMemoryBlock_	XilinxBlockRamGenerator	protected
SP_FILE	XilinxBlockRamGenerator	privatestatic
templatePath() const	MemoryGenerator	protected
ttaCoreName() const	MemoryGenerator	protected
warningStream()	MemoryGenerator	protected
warningStream_	MemoryGenerator	private
widthInMaus_	MemoryGenerator	private
XilinxBlockRamGenerator(int memMauWidth, int widthInMaus, int addrWidth, int portBDataWidth, int portBAddrWidth, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream, bool connectToArbiter=false, ProGe::NetlistBlock *almaifBlocks=nullptr, TCEString signalPrefix="", bool overrideAddrWidth=false, bool singleMemoryBlock=false)	XilinxBlockRamGenerator
~MemoryGenerator()	MemoryGenerator	virtual
~XilinxBlockRamGenerator()	XilinxBlockRamGenerator	virtual