XilinxBlockRamGenerator Class Reference

#include <XilinxBlockRamGenerator.hh>

Inheritance diagram for XilinxBlockRamGenerator:

Collaboration diagram for XilinxBlockRamGenerator:

Public Member Functions
	XilinxBlockRamGenerator (int memMauWidth, int widthInMaus, int addrWidth, int portBDataWidth, int portBAddrWidth, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream, bool connectToArbiter=false, ProGe::NetlistBlock *almaifBlocks=nullptr, TCEString signalPrefix="", bool overrideAddrWidth=false, bool singleMemoryBlock=false)
virtual	~XilinxBlockRamGenerator ()
virtual bool	generatesComponentHdlFile () const
virtual std::vector< TCEString >	generateComponentFile (TCEString outputPath)
virtual void	addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
virtual bool	isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const
Public Member Functions inherited from MemoryGenerator
	MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
virtual	~MemoryGenerator ()
int	memoryTotalWidth () const
int	memoryMauSize () const
int	memoryWidthInMaus () const
int	memoryAddrWidth () const
TCEString	initializationFile () const
void	addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

Protected Member Functions
virtual TCEString	moduleName () const
void	addPorts (std::string prefix, int addrWidth, int dataWidth)
virtual TCEString	instanceName (int coreId, int) const
TCEString	almaifPortName (const TCEString &portBaseName)
Protected Member Functions inherited from MemoryGenerator
virtual bool	checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const
virtual void	connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
virtual MemoryGenerator::BlockPair	createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
const PlatformIntegrator *	platformIntegrator () const
std::ostream &	warningStream ()
std::ostream &	errorStream ()
int	portCount () const
const HDLPort *	port (int index) const
const HDLPort *	portByKeyName (TCEString name) const
TCEString	portKeyName (const HDLPort *port) const
void	addPort (const TCEString &name, HDLPort *port)
int	parameterCount () const
const ProGe::Parameter &	parameter (int index) const
void	addParameter (const ProGe::Parameter &add)
TCEString	ttaCoreName () const
TCEString	memoryIndexString (int coreId, int memIndex) const
TCEString	templatePath () const
void	instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const
bool	hasLSUArchitecture () const
const TTAMachine::FunctionUnit &	lsuArchitecture () const
TCEString	corePortName (const TCEString &portBaseName, int coreId) const

Protected Attributes
const bool	connectToArbiter_
ProGe::NetlistBlock *	almaifBlock_
TCEString	signalPrefix_
const bool	overrideAddrWidth_
const bool	singleMemoryBlock_

Static Private Attributes
static const TCEString	DP_FILE = "xilinx_dp_blockram.vhdl"
static const TCEString	SP_FILE = "xilinx_blockram.vhdl"

Additional Inherited Members
Protected Types inherited from MemoryGenerator
typedef std::multimap< TCEString, HDLPort * >	PortMap
typedef std::pair< ProGe::NetlistBlock *, ProGe::VirtualNetlistBlock * >	BlockPair

Detailed Description

Definition at line 41 of file XilinxBlockRamGenerator.hh.

Constructor & Destructor Documentation

XilinxBlockRamGenerator()

XilinxBlockRamGenerator::XilinxBlockRamGenerator	(	int	memMauWidth,
		int	widthInMaus,
		int	addrWidth,
		int	portBDataWidth,
		int	portBAddrWidth,
		const PlatformIntegrator *	integrator,
		std::ostream &	warningStream,
		std::ostream &	errorStream,
		bool	connectToArbiter = false,
		ProGe::NetlistBlock *	almaifBlocks = nullptr,
		TCEString	signalPrefix = "",
		bool	overrideAddrWidth = false,
		bool	singleMemoryBlock = false
	)

Definition at line 47 of file XilinxBlockRamGenerator.cc.

    : MemoryGenerator(
          memMauWidth, widthInMaus, addrWidth, "", integrator, warningStream,
          errorStream),
      connectToArbiter_(connectToArbiter),
      almaifBlock_(almaifBlock),
      signalPrefix_(signalPrefix),
      overrideAddrWidth_(overrideAddrWidth),
      singleMemoryBlock_(singleMemoryBlock) {
    assert (!connectToArbiter || almaifBlock != nullptr);
 
    ProGe::Parameter dataw = {"dataw_g", "integer",
        Conversion::toString(memoryTotalWidth())};
    ProGe::Parameter addrw = {"addrw_g", "integer",
        Conversion::toString(memoryAddrWidth())};
 
 
    ProGe::Parameter second_dataw = {"dataw_b_g", "integer",
        Conversion::toString(portBDataWidth)};
    ProGe::Parameter second_addrw = {"addrw_b_g", "integer",
        Conversion::toString(portBAddrWidth)};
 
    if (overrideAddrWidth) {
        addrw.setValue("local_mem_addrw_g");
        second_addrw.setValue("local_mem_addrw_g");
    }
 
    addParameter(dataw);
    addParameter(addrw);
 
    if (connectToArbiter_) {
        addParameter(second_dataw);
        addParameter(second_addrw);
    }
 
    addPort("clk", new HDLPort("clk", "1", ProGe::BIT, ProGe::IN, false, 1));
    addPort("rstx", new HDLPort("rstx", "1", ProGe::BIT, ProGe::IN, false, 1));
    if (connectToArbiter) {
        addPorts("a_", memoryAddrWidth(), memoryTotalWidth());
        addPorts("b_", portBAddrWidth, portBDataWidth);
    } else {
        addPorts("", memoryAddrWidth(), memoryTotalWidth());
    }
}

References MemoryGenerator::addParameter(), MemoryGenerator::addPort(), addPorts(), assert, ProGe::BIT, connectToArbiter_, ProGe::IN, MemoryGenerator::memoryAddrWidth(), MemoryGenerator::memoryTotalWidth(), ProGe::Parameter::setValue(), and Conversion::toString().

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~XilinxBlockRamGenerator()

XilinxBlockRamGenerator::~XilinxBlockRamGenerator ( )

virtual

Definition at line 97 of file XilinxBlockRamGenerator.cc.

                                                  {
}

Member Function Documentation

addMemory()

void XilinxBlockRamGenerator::addMemory ( const ProGe::NetlistBlock &  ttaCore, ProGe::NetlistBlock &  integratorBlock, int  memIndex, int  coreId  )

virtual

Reimplemented from MemoryGenerator.

Definition at line 149 of file XilinxBlockRamGenerator.cc.

                              {
 
    // Do not instantiate multiple physical memories for shared AS when shared
    if (coreId > 0 && connectToArbiter_ && singleMemoryBlock_) {
        return;
    }
    BlockPair blocks =
        createMemoryNetlistBlock(integratorBlock, memIndex, coreId);
    ProGe::NetlistBlock* mem = blocks.first;
    ProGe::VirtualNetlistBlock* virt = blocks.second;
    assert(mem != NULL);
    assert(virt != NULL);
 
    if (virt->portCount() > 0) {
        integratorBlock.addSubBlock(virt);
    }
 
    for (int i = 0; i < portCount(); i++) {
        const HDLPort* hdlPort = port(i);
        ProGe::NetlistPort* memPort = mem->port(hdlPort->name());
        if (memPort == NULL) {
            memPort = virt->port(hdlPort->name());
            if (memPort == NULL) {
                TCEString msg = "Port ";
                msg << hdlPort->name() << " not found from netlist block";
                throw InvalidData(__FILE__, __LINE__, "MemoryGenerator", msg);
            }
        }
 
 
        TCEString portName = corePortName(portKeyName(hdlPort), coreId);
        const ProGe::NetlistPort* corePort = NULL;
        // clock and reset must be connected to new toplevel ports
        if (portName == platformIntegrator()->clockPort()->name()) {
            corePort = platformIntegrator()->clockPort();
        } else if (portName == platformIntegrator()->resetPort()->name()) {
            corePort = platformIntegrator()->resetPort();
        } else {
            if (connectToArbiter_) {
                portName = almaifPortName(portKeyName(hdlPort));
                corePort = almaifBlock_->port(portName);
            } else {
                corePort = ttaCore.port(portName);
            }
        }
        if (corePort == NULL) {
            TCEString msg = "Port ";
            msg << portName << " not found from";
            if (connectToArbiter_) {
                msg << " AlmaIF ";
            } else {
                msg << " TTA core ";
            }
            msg << "netlist block";
            throw InvalidData(__FILE__, __LINE__, "MemoryGenerator", msg);
        }
 
        if (connectToArbiter_ && !overrideAddrWidth_ &&
            corePort->realWidth() != memPort->realWidth()) {
            // Assume a private memory, split wide integrator signals accross
            // multiple cores
            int portWidth = memPort->realWidth();
            // This assumes no ports are inverted
            integratorBlock.netlist().connect(*memPort, *corePort,
                                              0, portWidth*coreId,
                                              portWidth);
        } else {
            connectPorts(
                integratorBlock, *corePort, *memPort,
                hdlPort->needsInversion(), coreId);
        }
    }
}

References ProGe::NetlistBlock::addSubBlock(), almaifBlock_, almaifPortName(), assert, PlatformIntegrator::clockPort(), ProGe::Netlist::connect(), MemoryGenerator::connectPorts(), connectToArbiter_, MemoryGenerator::corePortName(), MemoryGenerator::createMemoryNetlistBlock(), HDLPort::name(), HDLPort::needsInversion(), ProGe::NetlistBlock::netlist(), overrideAddrWidth_, MemoryGenerator::platformIntegrator(), ProGe::NetlistBlock::port(), MemoryGenerator::port(), ProGe::NetlistBlock::portCount(), MemoryGenerator::portCount(), MemoryGenerator::portKeyName(), ProGe::NetlistPort::realWidth(), PlatformIntegrator::resetPort(), and singleMemoryBlock_.

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addPorts()

void XilinxBlockRamGenerator::addPorts ( std::string  prefix, int  addrWidth, int  dataWidth  )

protected

Definition at line 106 of file XilinxBlockRamGenerator.cc.

                                                 {
    std::string datawGeneric = "dataw_g";
    std::string addrwGeneric = "addrw_g";
    if (pfx == "b_") {
        datawGeneric = "dataw_b_g";
        addrwGeneric = "addrw_b_g";
    }
    const ProGe::DataType BIT = ProGe::BIT;
    const ProGe::DataType VEC = ProGe::BIT_VECTOR;
    const ProGe::Direction IN  = ProGe::IN;
    const ProGe::Direction OUT = ProGe::OUT;
    const bool noInvert = false;
    addPort(pfx + "avalid_out",
            new HDLPort(pfx + "avalid_in", "1", BIT, IN, noInvert, 1));
    addPort(pfx + "aready_in",
            new HDLPort(pfx + "aready_out", "1", BIT, OUT, noInvert, 1));
    if (!overrideAddrWidth_) {
        addPort(pfx + "aaddr_out",
                new HDLPort(pfx + "aaddr_in", addrwGeneric, VEC, IN, noInvert,
                            addrWidth));
    } else {
        addPort(pfx + "aaddr_out",
                new HDLPort(pfx + "aaddr_in", addrwGeneric, VEC, IN, noInvert));
    }
    addPort(pfx + "awren_out",
            new HDLPort(pfx + "awren_in", "1", BIT, IN, noInvert, 1));
    addPort(pfx + "astrb_out",
            new HDLPort(pfx + "astrb_in", "(" + datawGeneric + "+7)/8", VEC, IN,
                        noInvert, (dataWidth+7)/8));
    addPort(pfx + "adata_out",
            new HDLPort(pfx + "adata_in", datawGeneric, VEC, IN, noInvert,
                        dataWidth));
    addPort(pfx + "rvalid_in",
            new HDLPort(pfx + "rvalid_out", "1", BIT, ProGe::OUT, noInvert, 1));
    addPort(pfx + "rready_out",
            new HDLPort(pfx + "rready_in", "1", BIT, IN, noInvert, 1));
    addPort(pfx + "rdata_in",
            new HDLPort(pfx + "rdata_out", datawGeneric, VEC, OUT, noInvert,
                        dataWidth));
}

References MemoryGenerator::addPort(), ProGe::BIT, ProGe::BIT_VECTOR, HDB::IN, ProGe::IN, HDB::OUT, ProGe::OUT, and overrideAddrWidth_.

Referenced by XilinxBlockRamGenerator().

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almaifPortName()

TCEString XilinxBlockRamGenerator::almaifPortName ( const TCEString &  portBaseName )

protected

Definition at line 263 of file XilinxBlockRamGenerator.cc.

                                                                     {
    // clock and reset port names are global
    if (portBaseName == platformIntegrator()->clockPort()->name() ||
        portBaseName == platformIntegrator()->resetPort()->name()) {
        return portBaseName;
    }
 
    return signalPrefix_ + "_" + portBaseName;
}

References MemoryGenerator::platformIntegrator(), and signalPrefix_.

Referenced by addMemory().

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generateComponentFile()

std::vector< TCEString > XilinxBlockRamGenerator::generateComponentFile ( TCEString  outputPath )

virtual

Implements MemoryGenerator.

Definition at line 227 of file XilinxBlockRamGenerator.cc.

                                                                   {
    TCEString inputFile =
        templatePath() << FileSystem::DIRECTORY_SEPARATOR
                       << (connectToArbiter_ ? DP_FILE : SP_FILE);
    TCEString outputFile;
    outputFile << outputPath << FileSystem::DIRECTORY_SEPARATOR
               << moduleName() << ".vhdl";
 
    FileSystem::copy(inputFile, outputPath);
    std::vector<TCEString> files;
    files.push_back(outputFile);
    return files;
}

References connectToArbiter_, FileSystem::copy(), FileSystem::DIRECTORY_SEPARATOR, DP_FILE, moduleName(), SP_FILE, and MemoryGenerator::templatePath().

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generatesComponentHdlFile()

bool XilinxBlockRamGenerator::generatesComponentHdlFile ( ) const

virtual

Implements MemoryGenerator.

Definition at line 101 of file XilinxBlockRamGenerator.cc.

                                                         {
    return true;
}

instanceName()

TCEString XilinxBlockRamGenerator::instanceName ( int  coreId, int    ) const

protectedvirtual

Implements MemoryGenerator.

Definition at line 253 of file XilinxBlockRamGenerator.cc.

                                                           {
    TCEString iname = "onchip_mem_";
 
    if (coreId != -1) {
        iname << "core" << coreId << "_";
    }
    return iname << signalPrefix_;
}

References signalPrefix_.

isCompatible()

bool XilinxBlockRamGenerator::isCompatible ( const ProGe::NetlistBlock &  ttaCore, int  coreId, std::vector< TCEString > &  reasons  ) const

virtual

Tests that the memory generator is compatible with TTA core. If incompatible, reasons are appended to the reasons vector

Parameters

ttaCore	TTA toplevel
coreId	The core ID number
reasons	Reasons why incompatible

Returns

is memory generator compatible with the TTA core

Reimplemented from MemoryGenerator.

Definition at line 274 of file XilinxBlockRamGenerator.cc.

                                                         {
    if (connectToArbiter_) {
        // TODO: Actually check almaifBlock_ ports?
        return true;
    } else {
        return MemoryGenerator::isCompatible(ttaCore, coreId, reasons);
    }
}

References connectToArbiter_, and MemoryGenerator::isCompatible().

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moduleName()

TCEString XilinxBlockRamGenerator::moduleName ( ) const

protectedvirtual

Implements MemoryGenerator.

Definition at line 243 of file XilinxBlockRamGenerator.cc.

                                          {
    TCEString name = "xilinx_";
    if (connectToArbiter_)
        name += "dp_";
    name += "blockram";
    return name;
}

References connectToArbiter_.

Referenced by generateComponentFile().

Member Data Documentation

almaifBlock_

ProGe::NetlistBlock* XilinxBlockRamGenerator::almaifBlock_

protected

Definition at line 82 of file XilinxBlockRamGenerator.hh.

Referenced by addMemory().

connectToArbiter_

const bool XilinxBlockRamGenerator::connectToArbiter_

protected

Definition at line 81 of file XilinxBlockRamGenerator.hh.

Referenced by addMemory(), generateComponentFile(), isCompatible(), moduleName(), and XilinxBlockRamGenerator().

DP_FILE

const TCEString XilinxBlockRamGenerator::DP_FILE = "xilinx_dp_blockram.vhdl"

staticprivate

Definition at line 89 of file XilinxBlockRamGenerator.hh.

Referenced by generateComponentFile().

overrideAddrWidth_

const bool XilinxBlockRamGenerator::overrideAddrWidth_

protected

Definition at line 84 of file XilinxBlockRamGenerator.hh.

Referenced by addMemory(), and addPorts().

signalPrefix_

TCEString XilinxBlockRamGenerator::signalPrefix_

protected

Definition at line 83 of file XilinxBlockRamGenerator.hh.

Referenced by almaifPortName(), and instanceName().

singleMemoryBlock_

const bool XilinxBlockRamGenerator::singleMemoryBlock_

protected

Definition at line 85 of file XilinxBlockRamGenerator.hh.

Referenced by addMemory().

SP_FILE

const TCEString XilinxBlockRamGenerator::SP_FILE = "xilinx_blockram.vhdl"

staticprivate

Definition at line 90 of file XilinxBlockRamGenerator.hh.

Referenced by generateComponentFile().

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The documentation for this class was generated from the following files:

• XilinxBlockRamGenerator.hh
• XilinxBlockRamGenerator.cc