#include <MemoryGenerator.hh>

Inheritance diagram for MemoryGenerator:

Collaboration diagram for MemoryGenerator:

Public Member Functions
	MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~MemoryGenerator ()

virtual bool	isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const

virtual void	addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

virtual bool	generatesComponentHdlFile () const =0

virtual std::vector< TCEString >	generateComponentFile (TCEString outputPath)=0

int	memoryTotalWidth () const

int	memoryMauSize () const

int	memoryWidthInMaus () const

int	memoryAddrWidth () const

TCEString	initializationFile () const

void	addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

Protected Types
typedef std::multimap< TCEString, HDLPort * >	PortMap

typedef std::pair< ProGe::NetlistBlock , ProGe::VirtualNetlistBlock >	BlockPair

Protected Member Functions
virtual bool	checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const

virtual void	connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)

virtual MemoryGenerator::BlockPair	createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

const PlatformIntegrator *	platformIntegrator () const

std::ostream &	warningStream ()

std::ostream &	errorStream ()

int	portCount () const

const HDLPort *	port (int index) const

const HDLPort *	portByKeyName (TCEString name) const

TCEString	portKeyName (const HDLPort *port) const

void	addPort (const TCEString &name, HDLPort *port)

int	parameterCount () const

const ProGe::Parameter &	parameter (int index) const

void	addParameter (const ProGe::Parameter &add)

TCEString	ttaCoreName () const

virtual TCEString	moduleName () const =0

virtual TCEString	instanceName (int coreId, int memIndex) const =0

TCEString	memoryIndexString (int coreId, int memIndex) const

TCEString	templatePath () const

void	instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const

bool	hasLSUArchitecture () const

const TTAMachine::FunctionUnit &	lsuArchitecture () const

TCEString	corePortName (const TCEString &portBaseName, int coreId) const

Private Types
typedef std::vector< ProGe::Parameter >	ParameterList

Private Attributes
int	mauWidth_

int	widthInMaus_

int	addrWidth_

TCEString	initFile_

const PlatformIntegrator *	integrator_

std::ostream &	warningStream_

std::ostream &	errorStream_

PortMap	memPorts_

ParameterList	params_

TTAMachine::FunctionUnit *	lsuArch_

std::vector< std::string >	lsuPorts_

Static Private Attributes
static const TCEString	CLOCK_PORT = "clk"

static const TCEString	RESET_PORT = "rstx"

Detailed Description

Definition at line 85 of file MemoryGenerator.hh.

Member Typedef Documentation

◆ BlockPair

typedef std::pair<ProGe::NetlistBlock*, ProGe::VirtualNetlistBlock*> MemoryGenerator::BlockPair

protected

Definition at line 148 of file MemoryGenerator.hh.

◆ ParameterList

typedef std::vector<ProGe::Parameter> MemoryGenerator::ParameterList

private

Definition at line 215 of file MemoryGenerator.hh.

◆ PortMap

typedef std::multimap<TCEString, HDLPort*> MemoryGenerator::PortMap

protected

Definition at line 145 of file MemoryGenerator.hh.

Constructor & Destructor Documentation

◆ MemoryGenerator()

MemoryGenerator::MemoryGenerator	(	int	memMauWidth,
		int	widthInMaus,
		int	addrWidth,
		TCEString	initFile,
		const PlatformIntegrator *	integrator,
		std::ostream &	warningStream,
		std::ostream &	errorStream
	)

Definition at line 59 of file MemoryGenerator.cc.

     : mauWidth_(mauWidth),
       widthInMaus_(widthInMaus),
       addrWidth_(addrWidth),
       initFile_(initFile),
       integrator_(integrator),
       warningStream_(warningStream),
       errorStream_(errorStream),
       lsuArch_(NULL),
       lsuPorts_() {}

◆ ~MemoryGenerator()

MemoryGenerator::~MemoryGenerator ( )

virtual

Definition at line 73 of file MemoryGenerator.cc.

                                   {
  
     for (PortMap::iterator i = memPorts_.begin(); i != memPorts_.end(); i++) {
         if (i->second != NULL)
             delete i->second;
     }
 }

References memPorts_.

Member Function Documentation

◆ addLsu()

void MemoryGenerator::addLsu	(	TTAMachine::FunctionUnit &	lsuArch,
		std::vector< std::string >	lsuPorts
	)

For data memories

Definition at line 376 of file MemoryGenerator.cc.

                                                                     {
     lsuArch_ = &lsuArch;
     lsuPorts_ = lsuPorts;
 }

References lsuArch_, and lsuPorts_.

Referenced by AlteraIntegrator::dmemInstance(), KoskiIntegrator::dmemInstance(), AlmaIFIntegrator::dmemInstance(), and Stratix2DSPBoardIntegrator::dmemInstance().

◆ addMemory()

void MemoryGenerator::addMemory	(	const ProGe::NetlistBlock &	ttaCore,
		ProGe::NetlistBlock &	integratorBlock,
		int	memIndex,
		int	coreId
	)

virtual

Reimplemented in AlteraOnchipRomGenerator, XilinxBlockRamGenerator, AlteraMemGenerator, Stratix2SramGenerator, and DummyMemGenerator.

Definition at line 119 of file MemoryGenerator.cc.

                               {
     BlockPair blocks =
         createMemoryNetlistBlock(integratorBlock, memIndex, coreId);
     NetlistBlock* mem = blocks.first;
     VirtualNetlistBlock* virt = blocks.second;
     assert(mem != NULL);
     assert(virt != NULL);
     if (virt->portCount() > 0) {
         integratorBlock.addSubBlock(virt);
     }
  
     for (int i = 0; i < portCount(); i++) {
         const HDLPort* hdlPort = port(i);
         NetlistPort* memPort = mem->port(hdlPort->name());
         if (memPort == NULL) {
             memPort = virt->port(hdlPort->name());
             if (memPort == NULL) {
                 TCEString msg = "Port ";
                 msg << hdlPort->name() << " not found from netlist block";
                 throw InvalidData(__FILE__, __LINE__, "MemoryGenerator", msg);
             }
         }
  
         TCEString portName = corePortName(portKeyName(hdlPort), coreId);
         const NetlistPort* corePort = NULL;
         // clock and reset must be connected to new toplevel ports
         if (portName == platformIntegrator()->clockPort()->name()) {
             corePort = platformIntegrator()->clockPort();
         } else if (portName == platformIntegrator()->resetPort()->name()) {
             corePort = platformIntegrator()->resetPort();
         } else {
             corePort = ttaCore.port(portName);
         }
         assert(corePort != NULL);
  
         connectPorts(
             integratorBlock, *memPort, *corePort, hdlPort->needsInversion(),
             coreId);
     }
 }

References ProGe::NetlistBlock::addSubBlock(), assert, PlatformIntegrator::clockPort(), connectPorts(), corePortName(), createMemoryNetlistBlock(), HDLPort::name(), HDLPort::needsInversion(), platformIntegrator(), ProGe::NetlistBlock::port(), port(), ProGe::NetlistBlock::portCount(), portCount(), portKeyName(), and PlatformIntegrator::resetPort().

Referenced by AlteraMemGenerator::addMemory(), AlteraOnchipRomGenerator::addMemory(), and PlatformIntegrator::generateMemory().

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◆ addParameter()

void MemoryGenerator::addParameter ( const ProGe::Parameter & add )

protected

Definition at line 313 of file MemoryGenerator.cc.

                                                        {
     ProGe::Parameter toAdd(add.name(), add.type(), add.value());
     params_.push_back(toAdd);
 }

References ProGe::Parameter::name(), params_, ProGe::Parameter::type(), and ProGe::Parameter::value().

Referenced by AlteraMemGenerator::addGenerics(), Stratix2SramGenerator::Stratix2SramGenerator(), VhdlRomGenerator::VhdlRomGenerator(), and XilinxBlockRamGenerator::XilinxBlockRamGenerator().

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◆ addPort()

void MemoryGenerator::addPort	(	const TCEString &	name,
		HDLPort *	port
	)

protected

Definition at line 294 of file MemoryGenerator.cc.

                                                              {
  
     assert(port != NULL);
     memPorts_.insert(std::pair<TCEString, HDLPort*>(name, port));
 }

References assert, memPorts_, and port().

Referenced by XilinxBlockRamGenerator::addPorts(), AlteraHibiDpRamGenerator::AlteraHibiDpRamGenerator(), AlteraOnchipRamGenerator::AlteraOnchipRamGenerator(), AlteraOnchipRomGenerator::AlteraOnchipRomGenerator(), Stratix2SramGenerator::Stratix2SramGenerator(), VhdlRomGenerator::VhdlRomGenerator(), and XilinxBlockRamGenerator::XilinxBlockRamGenerator().

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◆ checkFuPort()

bool MemoryGenerator::checkFuPort	(	const std::string	fuPort,
		std::vector< TCEString > &	reasons
	)		const

protectedvirtual

Reimplemented in DummyMemGenerator, and AlteraHibiDpRamGenerator.

Definition at line 106 of file MemoryGenerator.cc.

                                                                  {
     PortMap::const_iterator iter = memPorts_.find(fuPort);
     if (iter == memPorts_.end()) {
         TCEString msg;
         msg << "MemoryGenerator does not have port " << fuPort;
         reasons.push_back(msg);
         return false;
     }
     return true;
 }

References memPorts_.

Referenced by AlteraHibiDpRamGenerator::checkFuPort(), and isCompatible().

◆ connectPorts()

void MemoryGenerator::connectPorts	(	ProGe::NetlistBlock &	netlistBlock,
		const ProGe::NetlistPort &	memPort,
		const ProGe::NetlistPort &	corePort,
		bool	inverted,
		int	coreId
	)

protectedvirtual

Reimplemented in AlteraHibiDpRamGenerator.

Definition at line 392 of file MemoryGenerator.cc.

                                                             {
     if (inverted) {
         ProGe::InverterBlock* InvertedBlock =
             new ProGe::InverterBlock(corePort, memPort);
         netlistBlock.addSubBlock(InvertedBlock);
  
         netlistBlock.netlist().connect(
             corePort, InvertedBlock->inputPort(), 0, 0, 1);
         netlistBlock.netlist().connect(
             InvertedBlock->outputPort(), memPort, 0, 0, 1);
  
     } else {
         if (memPort.dataType() == corePort.dataType()) {
             netlistBlock.netlist().connect(memPort, corePort);
         } else {
             // bit to bit vector connection, connect lowest bits
             netlistBlock.netlist().connect(memPort, corePort, 0, 0, 1);
         }
     }
 }

References ProGe::NetlistBlock::addSubBlock(), ProGe::Netlist::connect(), ProGe::NetlistPort::dataType(), ProGe::InverterBlock::inputPort(), ProGe::NetlistBlock::netlist(), and ProGe::InverterBlock::outputPort().

Referenced by Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), addMemory(), and AlteraHibiDpRamGenerator::connectPorts().

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◆ corePortName()

TCEString MemoryGenerator::corePortName	(	const TCEString &	portBaseName,
		int	coreId
	)		const

protected

Definition at line 356 of file MemoryGenerator.cc.

                                                      {
     // clock and reset port names are global
     if (portBaseName == integrator_->clockPort()->name() ||
         portBaseName == integrator_->resetPort()->name()) {
         return portBaseName;
     }
  
     TCEString portName;
     if (coreId >= 0) {
         portName << "core" << coreId << "_";
     }
     if (lsuArch_ != NULL) {
         portName << "fu_" << lsuArchitecture().name() << "_";
     }
     portName << portBaseName;
     return portName;
 }

References PlatformIntegrator::clockPort(), integrator_, lsuArch_, lsuArchitecture(), TTAMachine::Component::name(), ProGe::NetlistPort::name(), and PlatformIntegrator::resetPort().

Referenced by Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), addMemory(), and isCompatible().

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◆ createMemoryNetlistBlock()

MemoryGenerator::BlockPair MemoryGenerator::createMemoryNetlistBlock	(	ProGe::NetlistBlock &	integratorBlock,
		int	memIndex,
		int	coreId
	)

protectedvirtual

Definition at line 163 of file MemoryGenerator.cc.

                                                                   {
     VirtualNetlistBlock* staticConnectionsBlock = new VirtualNetlistBlock(
         moduleName() + "_virt", instanceName(coreId, memIndex) + "_virt");
  
     NetlistBlock* mem =
         new NetlistBlock(moduleName(), instanceName(coreId, memIndex));
     integratorBlock.addSubBlock(mem);
  
     for (int i = 0; i < parameterCount(); i++) {
         mem->setParameter(parameter(i));
     }
     for (int i = 0; i < portCount(); i++) {
         const HDLPort* hdlPort = port(i);
         NetlistPort* memPort = NULL;
         if (hdlPort->hasStaticValue()) {
             memPort = hdlPort->convertToNetlistPort(*staticConnectionsBlock);
         } else {
             memPort = hdlPort->convertToNetlistPort(*mem);
         }
         assert(memPort != NULL);
     }
  
     BlockPair blocks;
     blocks.first = mem;
     blocks.second = staticConnectionsBlock;
     return blocks;
 }

References ProGe::NetlistBlock::addSubBlock(), assert, HDLPort::convertToNetlistPort(), HDLPort::hasStaticValue(), instanceName(), moduleName(), parameter(), parameterCount(), port(), portCount(), and ProGe::NetlistBlock::setParameter().

Referenced by XilinxBlockRamGenerator::addMemory(), and addMemory().

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◆ errorStream()

std::ostream & MemoryGenerator::errorStream ( )

protected

Definition at line 237 of file MemoryGenerator.cc.

                              {
  
     return errorStream_;
 }

References errorStream_.

◆ generateComponentFile()

virtual std::vector<TCEString> MemoryGenerator::generateComponentFile ( TCEString outputPath )

pure virtual

Implemented in DummyMemGenerator, Stratix2SramGenerator, AlteraHibiDpRamGenerator, AlteraOnchipRamGenerator, AlteraOnchipRomGenerator, VhdlRomGenerator, and XilinxBlockRamGenerator.

Referenced by PlatformIntegrator::generateMemory().

◆ generatesComponentHdlFile()

virtual bool MemoryGenerator::generatesComponentHdlFile ( ) const

pure virtual

Implemented in Stratix2SramGenerator, AlteraHibiDpRamGenerator, AlteraOnchipRamGenerator, AlteraOnchipRomGenerator, DummyMemGenerator, VhdlRomGenerator, and XilinxBlockRamGenerator.

Referenced by PlatformIntegrator::generateMemory().

◆ hasLSUArchitecture()

bool MemoryGenerator::hasLSUArchitecture ( ) const

protected

Definition at line 344 of file MemoryGenerator.cc.

                                           {
     return lsuArch_ != NULL;
 }

References lsuArch_.

◆ initializationFile()

TCEString MemoryGenerator::initializationFile ( ) const

Definition at line 219 of file MemoryGenerator.cc.

                                           {
     
     return initFile_;
 }

References initFile_.

Referenced by AlteraMemGenerator::addGenerics(), and VhdlRomGenerator::generateComponentFile().

◆ instanceName()

virtual TCEString MemoryGenerator::instanceName	(	int	coreId,
		int	memIndex
	)		const

protectedpure virtual

Implemented in DummyMemGenerator, XilinxBlockRamGenerator, AlteraHibiDpRamGenerator, AlteraOnchipRomGenerator, Stratix2SramGenerator, AlteraOnchipRamGenerator, and VhdlRomGenerator.

Referenced by AlteraMemGenerator::addGenerics(), and createMemoryNetlistBlock().

◆ instantiateTemplate()

void MemoryGenerator::instantiateTemplate	(	const TCEString &	inFile,
		const TCEString &	outFile,
		const TCEString &	entity
	)		const

protected

Definition at line 333 of file MemoryGenerator.cc.

                                    {
  
     HDLTemplateInstantiator inst;
     inst.setEntityString(entity);
     inst.instantiateTemplateFile(inFile, outFile);
 }

References HDLTemplateInstantiator::instantiateTemplateFile(), and HDLTemplateInstantiator::setEntityString().

Referenced by AlteraMemGenerator::instantiateAlteraTemplate().

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◆ isCompatible()

bool MemoryGenerator::isCompatible	(	const ProGe::NetlistBlock &	ttaCore,
		int	coreId,
		std::vector< TCEString > &	reasons
	)		const

virtual

Tests that the memory generator is compatible with TTA core. If incompatible, reasons are appended to the reasons vector

Parameters

ttaCore	TTA toplevel
coreId	The core ID number
reasons	Reasons why incompatible

Returns: is memory generator compatible with the TTA core

Reimplemented in XilinxBlockRamGenerator.

Definition at line 82 of file MemoryGenerator.cc.

                                          {
     for (std::string port : lsuPorts_) {
         if (!checkFuPort(port, reasons)) {
             return false;
         }
     }
     bool foundAll = true;
     PortMap::const_iterator iter = memPorts_.begin();
     while (iter != memPorts_.end()) {
         TCEString corePort = corePortName(iter->first, coreId);
         if (ttaCore.port(corePort) == NULL) {
             TCEString message = "Couldn't find port " + corePort +
                 " from toplevel";
             reasons.push_back(message);
             foundAll = false;
         }
         iter++;
     }
     return foundAll;
 }

References checkFuPort(), corePortName(), lsuPorts_, memPorts_, ProGe::NetlistBlock::port(), and port().

Referenced by PlatformIntegrator::generateMemory(), and XilinxBlockRamGenerator::isCompatible().

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◆ lsuArchitecture()

const TTAMachine::FunctionUnit & MemoryGenerator::lsuArchitecture ( ) const

protected

Definition at line 349 of file MemoryGenerator.cc.

                                        {
  
     assert(lsuArch_ != NULL);
     return *lsuArch_;
 }

References assert, and lsuArch_.

Referenced by corePortName().

◆ memoryAddrWidth()

int MemoryGenerator::memoryAddrWidth ( ) const

Definition at line 212 of file MemoryGenerator.cc.

                                        {
  
     return addrWidth_;
 }

References addrWidth_.

Referenced by AlteraMemGenerator::addMemory(), AlteraHibiDpRamGenerator::AlteraHibiDpRamGenerator(), AlteraOnchipRamGenerator::AlteraOnchipRamGenerator(), AlteraHibiDpRamGenerator::connectPorts(), VhdlRomGenerator::VhdlRomGenerator(), and XilinxBlockRamGenerator::XilinxBlockRamGenerator().

◆ memoryIndexString()

TCEString MemoryGenerator::memoryIndexString	(	int	coreId,
		int	memIndex
	)		const

protected

Definition at line 383 of file MemoryGenerator.cc.

                                                                  {
     TCEString index;
     if (coreId >= 0) {
         index << coreId << "_";
     }
     return index << memIndex;
 }

Referenced by VhdlRomGenerator::instanceName(), AlteraOnchipRamGenerator::instanceName(), Stratix2SramGenerator::instanceName(), AlteraOnchipRomGenerator::instanceName(), and AlteraHibiDpRamGenerator::instanceName().

◆ memoryMauSize()

int MemoryGenerator::memoryMauSize ( ) const

Definition at line 199 of file MemoryGenerator.cc.

                                      {
  
     return mauWidth_;
 }

References mauWidth_.

◆ memoryTotalWidth()

int MemoryGenerator::memoryTotalWidth ( ) const

Definition at line 193 of file MemoryGenerator.cc.

                                         {
  
     return mauWidth_*widthInMaus_;
 }

References mauWidth_, and widthInMaus_.

Referenced by AlteraMemGenerator::addMemory(), AlteraHibiDpRamGenerator::AlteraHibiDpRamGenerator(), AlteraOnchipRamGenerator::AlteraOnchipRamGenerator(), VhdlRomGenerator::VhdlRomGenerator(), and XilinxBlockRamGenerator::XilinxBlockRamGenerator().

◆ memoryWidthInMaus()

int MemoryGenerator::memoryWidthInMaus ( ) const

Definition at line 205 of file MemoryGenerator.cc.

                                          {
  
     return widthInMaus_;
 }

References widthInMaus_.

Referenced by AlteraHibiDpRamGenerator::AlteraHibiDpRamGenerator(), and AlteraOnchipRamGenerator::AlteraOnchipRamGenerator().

◆ moduleName()

virtual TCEString MemoryGenerator::moduleName ( ) const

protectedpure virtual

Implemented in AlteraHibiDpRamGenerator, XilinxBlockRamGenerator, AlteraOnchipRomGenerator, Stratix2SramGenerator, DummyMemGenerator, AlteraOnchipRamGenerator, and VhdlRomGenerator.

Referenced by createMemoryNetlistBlock(), and AlteraMemGenerator::instantiateAlteraTemplate().

◆ parameter()

const ProGe::Parameter & MemoryGenerator::parameter ( int index ) const

protected

Definition at line 308 of file MemoryGenerator.cc.

                                           {
     return params_.at(index);
 }

References params_.

Referenced by Stratix2SramGenerator::addMemory(), and createMemoryNetlistBlock().

◆ parameterCount()

int MemoryGenerator::parameterCount ( ) const

protected

Definition at line 302 of file MemoryGenerator.cc.

                                       {
  
     return params_.size();
 }

References params_.

Referenced by Stratix2SramGenerator::addMemory(), and createMemoryNetlistBlock().

◆ platformIntegrator()

const PlatformIntegrator * MemoryGenerator::platformIntegrator ( ) const

protected

Definition at line 225 of file MemoryGenerator.cc.

                                           {
  
     return integrator_;
 }

References integrator_.

Referenced by AlteraMemGenerator::addGenerics(), XilinxBlockRamGenerator::addMemory(), addMemory(), XilinxBlockRamGenerator::almaifPortName(), and ttaCoreName().

◆ port()

const HDLPort * MemoryGenerator::port ( int index ) const

protected

Definition at line 249 of file MemoryGenerator.cc.

                                      {
     
     if (index > static_cast<int>(memPorts_.size())) {
         TCEString message = "Index out of range";
         throw OutOfRange(__FILE__, __LINE__, "MemoryGenerator", message);
     }
     PortMap::const_iterator iter = memPorts_.begin();
     for (int i = 0; i < index; i++) {
         iter++;
     }
     return iter->second;
 }

References memPorts_.

Referenced by Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), addMemory(), addPort(), createMemoryNetlistBlock(), isCompatible(), and portKeyName().

◆ portByKeyName()

const HDLPort * MemoryGenerator::portByKeyName ( TCEString name ) const

protected

Definition at line 264 of file MemoryGenerator.cc.

                                                    {
  
     if (memPorts_.find(name) == memPorts_.end()) {
         TCEString message = "Port " + name + " not found";
         throw KeyNotFound(__FILE__, __LINE__, "MemoryGenerator", message);
     }
     return memPorts_.find(name)->second;
 }

References memPorts_.

◆ portCount()

int MemoryGenerator::portCount ( ) const

protected

Definition at line 243 of file MemoryGenerator.cc.

                                  {
  
     return memPorts_.size();
 }

References memPorts_.

Referenced by Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), addMemory(), and createMemoryNetlistBlock().

◆ portKeyName()

TCEString MemoryGenerator::portKeyName ( const HDLPort * port ) const

protected

Definition at line 275 of file MemoryGenerator.cc.

                                                       {
     
     TCEString name = "";
     PortMap::const_iterator iter = memPorts_.begin();
     while (iter != memPorts_.end()) {
         if (iter->second == port) {
             name = iter->first;
             break;
         }
         iter++;
     }
     if (name.empty()) {
         TCEString message = "Key for port " + port->name() + " not found";
         throw KeyNotFound(__FILE__, __LINE__, "MemoryGenerator", message);
     }
     return name;
 }

References memPorts_, HDLPort::name(), and port().

Referenced by Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), and addMemory().

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◆ templatePath()

TCEString MemoryGenerator::templatePath ( ) const

protected

Returns base path to template files.

Definition at line 325 of file MemoryGenerator.cc.

                                     {
     
     TCEString path = Environment::dataDirPath("ProGe");
     path << FileSystem::DIRECTORY_SEPARATOR << "platform";
     return path;
 }

References Environment::dataDirPath(), and FileSystem::DIRECTORY_SEPARATOR.

Referenced by XilinxBlockRamGenerator::generateComponentFile(), and AlteraMemGenerator::instantiateAlteraTemplate().

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◆ ttaCoreName()

TCEString MemoryGenerator::ttaCoreName ( ) const

protected

Definition at line 319 of file MemoryGenerator.cc.

                                    {
  
     return platformIntegrator()->coreEntityName();
 }

References PlatformIntegrator::coreEntityName(), and platformIntegrator().

Referenced by VhdlRomGenerator::imagePackageName(), AlteraMemGenerator::instantiateAlteraTemplate(), VhdlRomGenerator::moduleName(), AlteraOnchipRamGenerator::moduleName(), AlteraOnchipRomGenerator::moduleName(), and AlteraHibiDpRamGenerator::moduleName().

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◆ warningStream()

std::ostream & MemoryGenerator::warningStream ( )

protected

Definition at line 231 of file MemoryGenerator.cc.

                                {
  
     return warningStream_;
 }

References warningStream_.

Member Data Documentation

◆ addrWidth_

int MemoryGenerator::addrWidth_

private

Definition at line 219 of file MemoryGenerator.hh.

Referenced by memoryAddrWidth().

◆ CLOCK_PORT

const TCEString MemoryGenerator::CLOCK_PORT = "clk"

staticprivate

Definition at line 234 of file MemoryGenerator.hh.

◆ errorStream_

std::ostream& MemoryGenerator::errorStream_

private

Definition at line 226 of file MemoryGenerator.hh.

Referenced by errorStream().

◆ initFile_

TCEString MemoryGenerator::initFile_

private

Definition at line 221 of file MemoryGenerator.hh.

Referenced by initializationFile().

◆ integrator_

const PlatformIntegrator* MemoryGenerator::integrator_

private

Definition at line 223 of file MemoryGenerator.hh.

Referenced by corePortName(), and platformIntegrator().

◆ lsuArch_

TTAMachine::FunctionUnit* MemoryGenerator::lsuArch_

private

Definition at line 231 of file MemoryGenerator.hh.

Referenced by addLsu(), corePortName(), hasLSUArchitecture(), and lsuArchitecture().

◆ lsuPorts_

std::vector<std::string> MemoryGenerator::lsuPorts_

private

Definition at line 232 of file MemoryGenerator.hh.

Referenced by addLsu(), and isCompatible().

◆ mauWidth_

int MemoryGenerator::mauWidth_

private

Definition at line 217 of file MemoryGenerator.hh.

Referenced by memoryMauSize(), and memoryTotalWidth().

◆ memPorts_

PortMap MemoryGenerator::memPorts_

private

Definition at line 228 of file MemoryGenerator.hh.

Referenced by addPort(), checkFuPort(), isCompatible(), port(), portByKeyName(), portCount(), portKeyName(), and ~MemoryGenerator().

◆ params_

ParameterList MemoryGenerator::params_

private

Definition at line 229 of file MemoryGenerator.hh.

Referenced by addParameter(), parameter(), and parameterCount().

◆ RESET_PORT

const TCEString MemoryGenerator::RESET_PORT = "rstx"

staticprivate

Definition at line 235 of file MemoryGenerator.hh.

◆ warningStream_

std::ostream& MemoryGenerator::warningStream_

private

Definition at line 225 of file MemoryGenerator.hh.

Referenced by warningStream().

◆ widthInMaus_

int MemoryGenerator::widthInMaus_

private

Definition at line 218 of file MemoryGenerator.hh.

Referenced by memoryTotalWidth(), and memoryWidthInMaus().

The documentation for this class was generated from the following files:

Public Member Functions

Protected Types

Protected Member Functions

Private Types

Private Attributes

Static Private Attributes

Detailed Description

Member Typedef Documentation

◆ BlockPair

◆ ParameterList

◆ PortMap

Constructor & Destructor Documentation

◆ MemoryGenerator()

◆ ~MemoryGenerator()

Member Function Documentation

◆ addLsu()

◆ addMemory()

◆ addParameter()

◆ addPort()

◆ checkFuPort()

◆ connectPorts()

◆ corePortName()

◆ createMemoryNetlistBlock()

◆ errorStream()

◆ generateComponentFile()

◆ generatesComponentHdlFile()

◆ hasLSUArchitecture()

◆ initializationFile()

◆ instanceName()

◆ instantiateTemplate()

◆ isCompatible()

◆ lsuArchitecture()

◆ memoryAddrWidth()

◆ memoryIndexString()

◆ memoryMauSize()

◆ memoryTotalWidth()

◆ memoryWidthInMaus()

◆ moduleName()

◆ parameter()

◆ parameterCount()

◆ platformIntegrator()

◆ port()

◆ portByKeyName()

◆ portCount()

◆ portKeyName()

◆ templatePath()

◆ ttaCoreName()

◆ warningStream()

Member Data Documentation

◆ addrWidth_

◆ CLOCK_PORT

◆ errorStream_

◆ initFile_

◆ integrator_

◆ lsuArch_

◆ lsuPorts_

◆ mauWidth_

◆ memPorts_

◆ params_

◆ RESET_PORT

◆ warningStream_

◆ widthInMaus_