Achievements:

Tools:

• A hardware framework for the semi-automatic generation of a VLSI implementation of data processor.
• The MOVE compiler and simulator. The compiler frontend is based on the GNU C/C++ compiler. The backend contains a MOVE specific code scheduler, in order to exploit the available instruction level parallelism. Both compiler and simulator are retargetable to application specific MOVE processors.
• The application analysis and architecture synthesis tool. This tool currently accepts C code and generates among others information about required functionality and achievable performance speedups.

Designed TTAs:

• A small 3 bus prototype TTA: MiniMove (TUD-DIMES)
• A 4 bus 32 bits prototype TTA: MOVE32INT (TUD-DIMES)
• A 3 bus 16 bits prototype TTA: Phoenix (TUD-EuroChip), operational as coprocessor within a SUN workstation
• Three TTAs have been incorporated on a single MPEG2 decoding chip (SPASE Nijmegen)
• A TTA video signal stretcher (TNO-FEL)
• A TTA intelligent data logger (TNO-FEL)
• Wireless communication (spread spectrum) TTA: WISSCE (TUD), under design

Future plans:

Architecture synthesis area:

• Design and implement new design space exploration strategy, based entirely on connection removal.
• Automated search for special function unit opportunities.

Hardware synthesis area:

• Performance improvement by means of better control logic, improved function units, better placement and routing, and better cells.
• Chaining of basic function units.

Software synthesis area:

• Integrated register allocation and scheduling.
• Scheduling for local memories.
• Support for multiple word-lengths.

Image processor case study:

• Develop a showcase processor for Océ that can do grayscale ops and color conversion.

Partitioning area (multi-processing):

• Development of suitable partitioning algorithms.
• Extend the TTA template for heterogeneous multi-processor solutions.