1 INTRODUCTION

This is the user manual for TTA Co-design Environment (TCE) [TCE] [lpt]The document describes all the tools in the toolset, and a set of common use cases in the form of tutorials.

Fig.1.1 shows a simplified overview of TCE. TCE supports programs written in C/C++ and OpenCL. User can easily design new customized Transport-Triggered Architecture (TTA) processors, compile the program, analyze the performance, and generate HDL implementations of the designed processors. The generated application-specific processor HDL can be synthesized for example to an FPGA chip. Then, user can modify the application and upload new program image to continue development.

Figure 1.1: Overview of TTA Co-design Environment (TCE).

[width=10cm]eps/tce_overview

Application-specific instruction-set processor (ASIP) is a programmable processor which is tailored to certain application (domain). Hence, it can outperform general-purpose processors in terms of performance, area, and power. On the other hand, the programmability and the powerful ASIP tools should provide increased productivity in comparison to fixed function accelerator implementations, which offer the highest performance.

With TCE, TTA ASIP configuration, SW compilation, and simulation can be carried out in the order of minutes and hence most of the time can be reserved to application and architecture co-development. It is fast to iterate over new TTA configurations, e.g., change the number and type of function units (FU), configure interconnection network (IC), register files (RF), or experiment with special function units (custom operations).

Simple TTA designs with support for a couple of parallel arithmetic operations consume in the order of approx. 1000-5000 LUTs (look-up tables), which means that modern FPGA's can easily include even tens of TTA cores. The operating clock frequency can be optimized to match the soft cores offered by FPGA vendors.