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Contents
Contents
32 2006-10-25 2018-03-091000complete
TTA-based Co-design Environment v1.17
Contents
1
INTRODUCTION
1
Document Overview
2
Acronyms, Abbreviations and Definitions
3
Typographic Conventions Used in the Document
2
PROCESSOR DESIGN FLOW
1
Design Flow Overview
2
Main File Formats
1
Architecture Definition File (ADF)
2
TTA Program Exchange Format (TPEF)
3
Hardware Database (HDB)
4
Implementation Definition File (IDF)
5
Binary Encoding Map
6
Operation Set Abstraction Layer (OSAL) Files
7
Simulation Trace Database
8
Exploration Result Database
9
Summary of file types
3
TUTORIALS AND HOW-TOS
1
TCE Tour
1
The Sample Application
2
Starting Point Processor Architecture
3
Compiling and simulating
4
Increasing performance by adding resources
5
Analyzing the Potential Custom Operations
6
Creating the Custom Operation
7
Use the custom operation in C code.
8
Adding HDL implementation of the FU to the hardware database (HDB).
9
Generating the VHDL and memory images
10
Further acceleration by adding custom operation to large TTA
11
Final Words
2
From C to VHDL as Quickly as Possible
3
Hello TTA World!
4
Streaming I/O
1
Streaming I/O function units
5
Implementing Programs in Parallel Assembly Code
1
Preparations
2
Introduction to DCT
3
Introduction to TCE assembly
4
Implementing DCT on TCE assembly
1
Verifying the assembly program
6
Using multiple memories from C code
7
Running TTA on FPGA
1
Simplest example: No data memory
1
Introduction
2
Application
3
Create TTA processor core and instruction image
4
Final steps to FPGA
2
Second example: Adding data memory
1
Create TTA processor core and binary images
2
Towards FPGA
3
More to test
8
How to print from Altera FPGAs
1
Hello World 2.0
1
Examine the first version
2
Light weight printing
2
FPGA execution
1
Preparations
2
Generate the processor
3
Modifications for using alternative Altera FPGA boards
4
Synthesize and execute
3
Caveats in printing from FPGA
4
Summary
9
Designing Floating-point Processors with TCE
1
Restrictions
2
Single-precision Function Units
3
Half-precision Support
4
Half-precision Function Units
5
Benchmark results
6
Alternative bit widths
7
Processor Simulator and Floating Point Operations
10
Multi-TTA Designs
11
OpenCL Support
12
System-on-a-Chip design with AlmaIF Integrator
1
Generate the Processor
2
Create a New Vivado Project
3
Create a Block Design
4
Cleanup
5
Synthesis and Implementation
4
PROCESSOR DESIGN TOOLS
1
TTA Processor Designer (ProDe)
1
Starting ProDe
2
Function Unit Operation Dialog
2
Operation Set Abstraction Layer (OSAL) Tools
1
Operation Set Editor (OSEd)
1
Capabilities of the OSEd
2
Usage
2
Operation Behavior Module Builder (buildopset)
3
OSAL Tester (testosal)
3
OSAL files
1
Operation Properties
2
Operation Input Properties
3
Operation Output Properties
4
Operation DAG
5
Operation Behavior
6
Behavior Description language
4
OSAL search paths
5
Processor Generator (ProGe)
1
IC/Decoder Generators
6
Platform Integrator
7
Supported Platforms
1
Altera based devices
1
Stratix2DSP
2
Stratix3DevKit
3
AvalonIntegrator
4
KoskiIntegrator
2
AlmaIFIntegrator
8
Hardware Database Editor (HDB Editor)
1
Usage
1
Creating a new HDB file
2
Adding new components
3
Adding FU/RF HDL source files
4
Using SRAM based Register File Implementations
9
Hardware Database Tester
1
Usage
2
Test conditions
10
Processor unit tester
1
Usage
11
Function Unit Interface
1
Operation code order
2
Summary of interface ports
1
Input/Output operand ports
2
Input load ports
3
Operation code port
4
Control signals
3
Reserved keywords in generics
5
CODE GENERATION TOOLS
1
TCE Compiler
1
Usage of TCE compiler
1
Examples of usage
2
Custom operations
3
Endianess Mode
4
Known issues
2
Binary Encoding Map Generator (BEMGenerator)
1
Usage
3
Parallel Assembler and Disassembler
1
Usage of Disassembler
1
An example of the usage
2
Usage of Assembler
1
An example of the usage
3
Memory Areas
4
General Line Format
5
Allowed characters
6
Literals
7
Labels
8
Data Line
9
Code Line
10
Long Immediate Chunk
11
Data Transport
12
Register Port Specifier
13
Assembler Command Directives
14
Assembly Format Style
15
Error Conditions
16
Warning Conditions
17
Disambiguation Rules
4
Program Image Generator (PIG)
1
Usage
1
An example of the usage
2
Dictionary Compressor
1
Instruction Dictionary compressor
2
Move Slot Dictionary compressor
3
Defining New Code Compressors
4
Creating the Code Compressor Module
5
Building the Shared Object
5
TPEF Dumper (dumptpef)
1
Usage
6
CO-DESIGN TOOLS
1
Architecture Simulation and Debugging
1
Processor Simulator CLI (ttasim)
1
Usage
2
Fast Compiled Simulation Engine
1
Usage
2
ccache
3
distcc
3
Remote Debugger
4
Simulator Control Language
1
Initialization
2
Simulation Settings
3
Control of How the Simulation Runs
4
Examining and modifying Program Code and Data
5
Control Where and When to Stop Program Simulation
6
Specifying Files and Directories
7
Examining State of Target Processor and Simulation
8
Miscellaneous Support Commands and Features
9
Command and Value History Logs
5
Traces
1
Profile Data
6
Processor Simulator GUI (Proxim)
1
Usage
2
Profiling with Proxim
2
System Level Simulation with SystemC
1
Instantiating TTACores
2
Describing Detailed Operation Pipeline Simulation Models
3
Processor Cost/Performance Estimator (estimate)
1
Command Line Options
4
Automatic Design Space Explorer (explore)
1
Explorer Application format
2
Command Line Options
3
Explorer Plugin: ConnectionSweeper
4
Explorer Plugin: SimpleICOptimizer
5
Explorer Plugin: RemoveUnconnectedComponents
6
Explorer Plugin: GrowMachine
7
Explorer Plugin: ImmediateGenerator
8
Explorer Plugin: ImplementationSelector
9
Explorer Plugin: MinimizeMachine
10
Explorer Plugin: ADFCombiner
11
Explorer Plugin: VLIWConnectIC
7
PROCESSOR TEMPLATE
1
Architecture Template
1
Transport Triggered Architecture
2
Immediates/Constants
3
Operations, Function Units, and Operand Bindings
4
Datapath Connectivity Levels
2
Programmer Interface
1
Default Data Address Space Layout
2
Instruction Address Space
3
Alignment of Words in Memory
4
Stack Frame Layout
5
Word Byte Order
6
Function Calling Conventions
7
Register Context Saving Conventions
8
PRODUCING EFFICIENT TTA DESIGNS WITH TCE
1
Registers and Register Files
2
Interconnection Network
1
Negative short immediates
3
Operation Set
9
TROUBLESHOOTING
1
Simulation
1
Failing to Load Operation Behavior Definitions
2
Limitations of the Current Toolset Version
1
Integer Width
2
Instruction Addressing During Simulation
3
Data Memory Addressing
4
Ideal Memory Model in Simulation
5
Guards
6
Operation Pipeline Description Limitations
7
Encoding of XML Files
8
Floating Point Support
A. FREQUENTLY ASKED QUESTIONS
1
Memory Related
1
Load Store Unit
2
Processor Generator
1
Warning: Processor Generator failed to generate a test bench
2
Warning: Opcode defined in HDB for operation ...
3
RTL simulation uses vast amounts of memory or crashes
3
tcecc
1
Disappearing code
4
Hardware characteristics
1
Interrupt support
5
Misc
1
File Search Paths
B. SystemC Simulation Example
C. Copyright notices
1
Xerces
2
wxWidgets
3
L-GPL
4
TCL
5
SQLite
6
Editline
Bibliography
About this document ...
Pekka Jääskeläinen 2018-03-12
