OpenASIP 2.2
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BinaryOps.hh
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1/*
2 Copyright (c) 2002-2017 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25* @file BinaryOps.hh
26*
27* @author Lasse Lehtonen 2017 (lasse.lehtonen-no.spam-tut.fi)
28*/
29#pragma once
30#include <LHSValue.hh>
31#include <HWGenTools.hh>
32#include <iostream>
33#include <string>
34
35namespace HDLGenerator {
36
37 class BinaryOp : public LHSValue {
38 public:
39 BinaryOp(const LHSValue& lhs, const LHSValue& rhs,
40 std::string VHDLOperator,
41 std::string VerilogOperator) {
42 vhdl_ = "(" + lhs.vhdl() + " " + VHDLOperator
43 + " " + rhs.vhdl() + ")";
44 verilog_ = "(" + lhs.verilog() + " " + VerilogOperator + " "
45 + rhs.verilog() + ")";
48 }
49 };
50
51 class LogicalAnd : public BinaryOp {
52 public:
53 LogicalAnd(const LHSValue& lhs, const LHSValue& rhs) :
54 BinaryOp(lhs, rhs, "and", "&") {}
55 };
56
57 class BitwiseAnd : public BinaryOp {
58 public:
59 BitwiseAnd(const LHSValue& lhs, const LHSValue& rhs) :
60 BinaryOp(lhs, rhs, "and", "&") {}
61 };
62
63 class LogicalOr : public BinaryOp {
64 public:
65 LogicalOr(const LHSValue& lhs, const LHSValue& rhs) :
66 BinaryOp(lhs, rhs, "or", "||") {}
67 };
68
69 class BitwiseOr : public BinaryOp {
70 public:
71 BitwiseOr(const LHSValue& lhs, const LHSValue& rhs) :
72 BinaryOp(lhs, rhs, "or", "|") {}
73 };
74
75 class BitwiseXor : public BinaryOp {
76 public:
77 BitwiseXor(const LHSValue& lhs, const LHSValue& rhs) :
78 BinaryOp(lhs, rhs, "xor", "^") {}
79 };
80
81 class Equals : public BinaryOp {
82 public:
83 Equals(const LHSValue& lhs, const LHSValue& rhs) :
84 BinaryOp(lhs, rhs, "=", "==") {}
85 };
86
87 class NotEquals : public BinaryOp {
88 public:
89 NotEquals(const LHSValue& lhs, const LHSValue& rhs) :
90 BinaryOp(lhs, rhs, "/=", "!=") {}
91 };
92
93 class UnaryOp : public LHSValue {
94 public:
95 UnaryOp(LHSValue val, std::string VHDLOperator,
96 std::string vlogOperator) {
97 vhdl_ = "(" + VHDLOperator + " " + val.vhdl() + ")";
98 verilog_ = "(" + vlogOperator + " " + val.verilog() + ")";
100 }
101 };
102
103 class LogicalNot : public UnaryOp {
104 public:
105 LogicalNot(LHSValue val) : UnaryOp(val, "not", "!") {}
106 };
107
108 class BitwiseNot : public UnaryOp {
109 public:
110 BitwiseNot(LHSValue val) : UnaryOp(val, "not", "~") {}
111 };
112
113 class Reduce : public LHSValue {
114 public:
115 Reduce(LHSValue val, std::string VHDLFunction,
116 std::string VerilogOperator) {
117 vhdl_ = VHDLFunction + "(" + val.vhdl() + ")";
118 verilog_ = "(" + VerilogOperator + " " + val.verilog() + ")";
120 }
121 };
122
123 class OrReduce : public Reduce {
124 public:
125 OrReduce(LHSValue val) : Reduce(val, "or_reduce", "|") {}
126 };
127
128 class AndReduce : public Reduce {
129 public:
130 AndReduce(LHSValue val) : Reduce(val, "and_reduce", "&") {}
131 };
132
133 class XorReduce : public Reduce {
134 public:
135 XorReduce(LHSValue val) : Reduce(val, "xor_reduce", "^") {}
136 };
137
138}
AndReduce(LHSValue val)
Definition BinaryOps.hh:130
BinaryOp(const LHSValue &lhs, const LHSValue &rhs, std::string VHDLOperator, std::string VerilogOperator)
Definition BinaryOps.hh:39
BitwiseAnd(const LHSValue &lhs, const LHSValue &rhs)
Definition BinaryOps.hh:59
BitwiseNot(LHSValue val)
Definition BinaryOps.hh:110
BitwiseOr(const LHSValue &lhs, const LHSValue &rhs)
Definition BinaryOps.hh:71
BitwiseXor(const LHSValue &lhs, const LHSValue &rhs)
Definition BinaryOps.hh:77
Equals(const LHSValue &lhs, const LHSValue &rhs)
Definition BinaryOps.hh:83
std::string vhdl() const
Definition LHSValue.hh:45
std::string verilog_
Definition LHSValue.hh:60
std::string verilog() const
Definition LHSValue.hh:46
std::unordered_set< std::string > readList_
Definition LHSValue.hh:58
void writeSignals(std::unordered_set< std::string > &readList) const
Definition LHSValue.cc:52
LogicalAnd(const LHSValue &lhs, const LHSValue &rhs)
Definition BinaryOps.hh:53
LogicalNot(LHSValue val)
Definition BinaryOps.hh:105
LogicalOr(const LHSValue &lhs, const LHSValue &rhs)
Definition BinaryOps.hh:65
NotEquals(const LHSValue &lhs, const LHSValue &rhs)
Definition BinaryOps.hh:89
OrReduce(LHSValue val)
Definition BinaryOps.hh:125
Reduce(LHSValue val, std::string VHDLFunction, std::string VerilogOperator)
Definition BinaryOps.hh:115
UnaryOp(LHSValue val, std::string VHDLOperator, std::string vlogOperator)
Definition BinaryOps.hh:95
XorReduce(LHSValue val)
Definition BinaryOps.hh:135