OpenASIP 2.2
|
Classes | |
class | AndReduce |
class | Assign |
class | Asynchronous |
class | Behaviour |
class | BinaryConstant |
class | BinaryLiteral |
class | BinaryOp |
class | BitwiseAnd |
class | BitwiseNot |
class | BitwiseOr |
class | BitwiseXor |
class | Case |
class | CodeBlock |
class | DefaultAssign |
class | DefaultCase |
class | Equals |
class | Ext |
class | Generatable |
class | HDLOperation |
class | If |
class | InPort |
class | IntegerConstant |
class | LHSSignal |
class | LHSValue |
class | LogicalAnd |
class | LogicalNot |
class | LogicalOr |
class | LogicVariable |
class | Module |
class | NewLine |
class | NotEquals |
class | Option |
class | OrReduce |
class | OutPort |
class | Parameter |
class | Port |
class | RawCodeLine |
class | Reduce |
class | Register |
class | SequentialStatement |
class | Sext |
class | SignedVariable |
class | Splice |
class | Switch |
class | Synchronous |
class | UnaryOp |
class | UnsignedVariable |
class | Variable |
struct | Width |
class | Wire |
class | XorReduce |
Enumerations | |
enum class | Language { VHDL , Verilog } |
enum class | WireType { Auto , Vector } |
enum class | Direction { In , Out } |
enum class | ResetOption { Mandatory , Optional } |
|
strong |
Enumerator | |
---|---|
In | |
Out |
Definition at line 35 of file HWGenTools.hh.
|
strong |
|
strong |
|
strong |
Enumerator | |
---|---|
Auto | |
Vector |
Definition at line 34 of file HWGenTools.hh.