53 target_(&targetRegister) {
54 assert(latency &&
"Use DirectGuardState for 0-cycle latency");
55 for (
int i = 0; i < latency; ++i) {
143 target_(&targetRegister) {
#define assert(condition)
virtual void advanceClock()
const ReadableState * target_
The target register watched by this guard.
virtual const SimValue & value() const
virtual ~DirectGuardState()
std::vector< SimValue > history_
Value history ring buffer.
const ReadableState * target_
The target register watched by this guard.
virtual const SimValue & value() const
virtual void advanceClock()
GuardState()
Only subclasses allowed to create empty GuardStates.
int position_
History ring buffer position. Point to the index of the current value of the guard.
static NullGuardState instance_
Unique instance of NullGuardState (singleton).
static NullGuardState & instance()
virtual ~NullGuardState()
virtual const SimValue & value() const =0