OpenASIP 2.2
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GuardState.hh
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1/*
2 Copyright (c) 2002-2009 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file GuardState.hh
26 *
27 * Declaration of GuardState class.
28 *
29 * @author Pekka Jääskeläinen 2006 (pjaaskel-no.spam-cs.tut.fi)
30 * @note rating: red
31 */
32
33#ifndef TTA_GUARD_STATE_HH
34#define TTA_GUARD_STATE_HH
35
36#include <vector>
37
38#include "ClockedState.hh"
39#include "ReadableState.hh"
40
41class GlobalLock;
42
43//////////////////////////////////////////////////////////////////////////////
44// GuardState
45//////////////////////////////////////////////////////////////////////////////
46
47/**
48 * Models the programmer visible delay of guards with latency more than 1.
49 *
50 * GuardState with latency of 1 is the default latency which can be modeled
51 * with a direct reference to the guarded register, thus this class should
52 * not be used to model such cases. Guard latency of 1 means that the guard
53 * value can be used in the same instruction in which the value itself can
54 * be used. Thus, in case of a register guard, the instruction following the
55 * write to the register. For example, guard with latency of 2 means that there
56 * is one instruction cycle after updating the value of the guard in which
57 * the new value is not yet visible, and so on. This latency is modeled with
58 * a ring buffer which represents the history of guard's target values.
59 */
60class GuardState : public ClockedState, public ReadableState {
61public:
63 const ReadableState& targetRegister,
64 int latency);
65
66 virtual ~GuardState();
67
68 virtual const SimValue& value() const;
69
70 virtual void endClock();
71 virtual void advanceClock();
72
73protected:
74 /// Only subclasses allowed to create empty GuardStates
75 GuardState();
76
77private:
78
79 /// Copying not allowed.
81 /// Assignment not allowed.
83 /// The target register watched by this guard.
85 /// Value history ring buffer.
86 std::vector<SimValue> history_;
87 /// History ring buffer position. Point to the index of the current
88 /// value of the guard.
90};
91
92//////////////////////////////////////////////////////////////////////////////
93// NullGuardState
94//////////////////////////////////////////////////////////////////////////////
95
96/**
97 * Models non-existing GuardState.
98 */
99class NullGuardState : public GuardState {
100public:
101 static NullGuardState& instance();
102
103 virtual ~NullGuardState();
104
105private:
107 /// Copying not allowed.
109 /// Assignment not allowed.
111
112 /// Unique instance of NullGuardState (singleton).
114};
115
116//////////////////////////////////////////////////////////////////////////////
117// OneClockGuardState
118//////////////////////////////////////////////////////////////////////////////
119/**
120 * Models a GuardState that reads value immediately from the source.
121 * Register guard latency 1 or port guard latency 0
122 */
124public:
125 DirectGuardState(const ReadableState& targetRegister);
126
127 virtual ~DirectGuardState();
128
129 virtual const SimValue& value() const;
130
131 virtual void endClock();
132 virtual void advanceClock();
133
134private:
136 /// Copying not allowed.
138 /// Assignment not allowed.
140
141 /// The target register watched by this guard.
143};
144
145#endif
DirectGuardState(const DirectGuardState &)
Copying not allowed.
virtual void endClock()
virtual void advanceClock()
const ReadableState * target_
The target register watched by this guard.
virtual const SimValue & value() const
DirectGuardState & operator=(const DirectGuardState &)
Assignment not allowed.
virtual ~DirectGuardState()
std::vector< SimValue > history_
Value history ring buffer.
Definition GuardState.hh:86
GuardState(const GuardState &)
Copying not allowed.
const ReadableState * target_
The target register watched by this guard.
Definition GuardState.hh:84
virtual const SimValue & value() const
virtual void endClock()
Definition GuardState.cc:82
virtual void advanceClock()
Definition GuardState.cc:89
GuardState & operator=(const GuardState &)
Assignment not allowed.
GuardState()
Only subclasses allowed to create empty GuardStates.
Definition GuardState.cc:67
virtual ~GuardState()
Definition GuardState.cc:73
int position_
History ring buffer position. Point to the index of the current value of the guard.
Definition GuardState.hh:89
static NullGuardState instance_
Unique instance of NullGuardState (singleton).
NullGuardState(const NullGuardState &)
Copying not allowed.
static NullGuardState & instance()
virtual ~NullGuardState()
NullGuardState & operator=(const NullGuardState &)
Assignment not allowed.