OpenASIP 2.2
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IGenerationPhases.hh
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * @file IGenerationPhases.hh
26 *
27 * Declaration of IGenerationPhases class.
28 *
29 * Created on: 20.4.2015
30 * @author: Henry Linjamäki (henry.linjamaki-no.spam-tut.fi)
31 * @note rating: red
32 */
33
34#ifndef IGENERATIONPHASES_HH
35#define IGENERATIONPHASES_HH
36
37#include "ProGeTypes.hh"
38#include "TCEString.hh"
39#include "Exception.hh"
40
41class Path;
42
43namespace ProGe {
44
46public:
47 virtual ~IGenerationPhases() {}
48
49 virtual void build() = 0;
50 virtual void connect() = 0;
51 virtual void finalize() = 0;
52 virtual void write(
53 const Path& targetBaseDir, HDL targetLang = VHDL) const = 0;
54};
55
56
57} // namespace ProGe
58
59#endif /* IGENERATIONPHASES_HH */
virtual void connect()=0
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const =0
virtual void build()=0
virtual void finalize()=0
Definition FUGen.hh:54
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40
@ VHDL
VHDL.
Definition ProGeTypes.hh:41