OpenASIP 2.2
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LongImmediateUnitState.hh
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1/*
2 Copyright (c) 2002-2009 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file LongImmediateUnitState.hh
26 *
27 * Declaration of LongImmediateUnitState class.
28 *
29 * @author Jussi Nykänen 2004 (nykanen-no.spam-cs.tut.fi)
30 * @author Pekka Jääskeläinen 2005 (pjaaskel-no.spam-cs.tut.fi)
31 * @note rating: red
32 */
33
34#ifndef TTA_LONG_IMMEDIATE_UNIT_STATE_HH
35#define TTA_LONG_IMMEDIATE_UNIT_STATE_HH
36
37#include <vector>
38#include <queue>
39#include <map>
40#include <string>
41
42#include "ClockedState.hh"
43#include "Exception.hh"
44#include "SimValue.hh"
45
47
48//////////////////////////////////////////////////////////////////////////////
49// LongImmediateUnitState
50//////////////////////////////////////////////////////////////////////////////
51
52/**
53 * Class that represents the states of long immediate units.
54 */
56public:
58 int size,
59 int latency,
60 const std::string& name,
61 int width,
62 bool signExtend);
64
65 virtual SimValue& registerValue(int index);
66 virtual void setRegisterValue(int index, const SimValue& value);
67
69 virtual int immediateRegisterCount() const;
70
71 virtual void endClock();
72 virtual void advanceClock();
73
74private:
75 /// Copying not allowed.
77 /// Assignment not allowed.
79
80 void clear();
81
82 /**
83 * Represents one value update request.
84 */
85 struct Item {
86 /**
87 * Constructor.
88 */
89 Item() : arrival_(0), value_(64), index_(0) {}
90 Item(SimValue value, int index, unsigned arrival)
91 : arrival_(arrival), value_(value), index_(index) {}
92
93 /// Timer of the item.
94 unsigned arrival_;
95 /// Value of the item.
97 /// Index of the item.
98 int index_;
99 };
100
101 typedef std::queue<Item> ItemQueue;
102 typedef std::vector<LongImmediateRegisterState*> RegisterContainer;
103 typedef std::vector<SimValue> ValueContainer;
104
105 /// Latency of LongImmediateUnit.
107 /// Name of the unit.
108 std::string name_;
109 /// Queue of register value update requests.
111 /// Contains all long immediate registers of the unit.
113 /// Contains all values of the registers.
115 /// Counter to time arrival of immediate values. Note: value is expected
116 /// to wrap.
117 unsigned timer_ = 0;
118
119};
120
121//////////////////////////////////////////////////////////////////////////////
122// NullLongImmediateUnitState
123//////////////////////////////////////////////////////////////////////////////
124
125/**
126 * Models non-existing LongImmediateUnitState.
127 */
129public:
131
133
134 virtual SimValue& registerValue(int index);
135 virtual void setRegisterValue(int index, const SimValue& value);
136
138 virtual int immediateRegisterCount() const;
139
140 virtual void endClock();
141 virtual void advanceClock();
142
143private:
145 /// Copying not allowed.
147 /// Assignment not allowed.
149
150 /// Unique instance of NullLongImmediateUnitState.
152};
153
154#endif
virtual LongImmediateRegisterState & immediateRegister(int i)
std::vector< SimValue > ValueContainer
virtual int immediateRegisterCount() const
ItemQueue queue_
Queue of register value update requests.
unsigned timer_
Counter to time arrival of immediate values. Note: value is expected to wrap.
LongImmediateUnitState & operator=(const LongImmediateUnitState &)
Assignment not allowed.
ValueContainer values_
Contains all values of the registers.
virtual void setRegisterValue(int index, const SimValue &value)
std::string name_
Name of the unit.
virtual SimValue & registerValue(int index)
int latency_
Latency of LongImmediateUnit.
RegisterContainer registers_
Contains all long immediate registers of the unit.
std::vector< LongImmediateRegisterState * > RegisterContainer
LongImmediateUnitState(const LongImmediateUnitState &)
Copying not allowed.
virtual SimValue & registerValue(int index)
NullLongImmediateUnitState(const NullLongImmediateUnitState &)
Copying not allowed.
virtual int immediateRegisterCount() const
static NullLongImmediateUnitState * instance_
Unique instance of NullLongImmediateUnitState.
NullLongImmediateUnitState & operator=(const NullLongImmediateUnitState &)
Assignment not allowed.
static NullLongImmediateUnitState & instance()
virtual void setRegisterValue(int index, const SimValue &value)
virtual LongImmediateRegisterState & immediateRegister(int i)
unsigned arrival_
Timer of the item.
Item(SimValue value, int index, unsigned arrival)
SimValue value_
Value of the item.