OpenASIP 2.2
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SimulationController.hh
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1/*
2 Copyright (c) 2002-2010 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file SimulationController.hh
26 *
27 * Declaration of SimulationController class.
28 *
29 * @author Jussi Nykänen 2005 (nykanen-no.spam-cs.tut.fi)
30 * @author Pekka Jääskeläinen 2005,2010 (pjaaskel-no.spam-cs.tut.fi)
31 * @note rating: red
32 */
33
34#ifndef SIMULATION_CONTROLLER_HH
35#define SIMULATION_CONTROLLER_HH
36
38
39/**
40 * Controls the simulation running in stand-alone mode.
41 *
42 * Supports also homogeneous multicore simulation when ADF's core-count > 1.
43 *
44 * Owns and is the main client of the machine state model.
45 */
47public:
48
53 bool fuResourceConflictDetection = true,
54 bool detailedSimulation = false);
55
56 virtual ~SimulationController();
57
58 virtual void step(double count = 1);
59
60 virtual void next(int count = 1);
61
62 virtual void run();
63
64 virtual void runUntil(UIntWord address);
65
66 virtual void reset();
67
68 virtual InstructionAddress programCounter() const;
69
70 virtual MachineState& machineState(int core=-1);
71 virtual const InstructionMemory& instructionMemory(int core=-1) const;
72
73 virtual std::string registerFileValue(
74 const std::string& rfName,
75 int registerIndex = -1);
76
78 const std::string& iuName, int index = -1);
79
80 virtual SimValue FUPortValue(
81 const std::string& fuName,
82 const std::string& portName);
83
84protected:
85 virtual bool simulateCycle();
86
87 typedef std::vector<MachineState*> MachineStateContainer;
88
89 /// The machine state models for the simulated cores.
91 /// The instruction memory models of cores.
92 std::vector<InstructionMemory*> instructionMemories_;
93
94private:
95 /// Copying not allowed.
97 /// Assignment not allowed.
99
101 void findExitPoints(
104
107
108 /// The FU resource conflict detectors used to detect conflicts during
109 /// simulation.
111 /// Resource conflict detectors in a more quickly traversed container.
112 std::vector<FUResourceConflictDetector*> conflictDetectorVector_;
113 /// Temporary place for lastExecuted Instruction.
114 std::vector<InstructionAddress> tmpExecutedInstructions_;
115
116};
117
118#endif
Word UIntWord
Definition BaseType.hh:144
UInt32 InstructionAddress
Definition BaseType.hh:175
TTAMachine::Machine * machine
the architecture definition of the estimated processor
std::vector< FUConflictDetectorIndex > MultiCoreFUConflictDetectorIndex
find Finds info of the inner loops in the program
std::vector< FUResourceConflictDetector * > conflictDetectorVector_
Resource conflict detectors in a more quickly traversed container.
void findExitPoints(const TTAProgram::Program &program, const TTAMachine::Machine &machine)
MachineStateContainer machineStates_
The machine state models for the simulated cores.
InstructionMemory & selectedInstructionMemory()
virtual void runUntil(UIntWord address)
SimulationController(const SimulationController &)
Copying not allowed.
virtual SimValue immediateUnitRegisterValue(const std::string &iuName, int index=-1)
std::vector< InstructionAddress > tmpExecutedInstructions_
Temporary place for lastExecuted Instruction.
virtual void next(int count=1)
virtual void step(double count=1)
virtual const InstructionMemory & instructionMemory(int core=-1) const
MachineState & selectedMachineState()
virtual std::string registerFileValue(const std::string &rfName, int registerIndex=-1)
SimulationController & operator=(const SimulationController &)
Assignment not allowed.
virtual InstructionAddress programCounter() const
std::vector< MachineState * > MachineStateContainer
std::vector< InstructionMemory * > instructionMemories_
The instruction memory models of cores.
virtual MachineState & machineState(int core=-1)
void buildFUResourceConflictDetectors(const TTAMachine::Machine &machine)
MultiCoreFUConflictDetectorIndex fuConflictDetectors_
The FU resource conflict detectors used to detect conflicts during simulation.
virtual SimValue FUPortValue(const std::string &fuName, const std::string &portName)
virtual SimulatorFrontend & frontend()