OpenASIP  2.0
IGenerationPhases.hh
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1 /*
2  Copyright (c) 2002-2015 Tampere University.
3 
4  This file is part of TTA-Based Codesign Environment (TCE).
5 
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24 /*
25  * @file IGenerationPhases.hh
26  *
27  * Declaration of IGenerationPhases class.
28  *
29  * Created on: 20.4.2015
30  * @author: Henry Linjamäki (henry.linjamaki-no.spam-tut.fi)
31  * @note rating: red
32  */
33 
34 #ifndef IGENERATIONPHASES_HH
35 #define IGENERATIONPHASES_HH
36 
37 #include "ProGeTypes.hh"
38 #include "TCEString.hh"
39 #include "Exception.hh"
40 
41 class Path;
42 
43 namespace ProGe {
44 
46 public:
47  virtual ~IGenerationPhases() {}
48 
49  virtual void build() = 0;
50  virtual void connect() = 0;
51  virtual void finalize() = 0;
52  virtual void write(
53  const Path& targetBaseDir, HDL targetLang = VHDL) const = 0;
54 };
55 
56 
57 } // namespace ProGe
58 
59 #endif /* IGENERATIONPHASES_HH */
Path
Definition: FileSystem.hh:197
Exception.hh
ProGe::IGenerationPhases::~IGenerationPhases
virtual ~IGenerationPhases()
Definition: IGenerationPhases.hh:47
ProGe::IGenerationPhases::finalize
virtual void finalize()=0
ProGe::IGenerationPhases
Definition: IGenerationPhases.hh:45
TCEString.hh
ProGe::VHDL
@ VHDL
VHDL.
Definition: ProGeTypes.hh:41
ProGeTypes.hh
ProGe::IGenerationPhases::connect
virtual void connect()=0
ProGe::IGenerationPhases::write
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const =0
ProGe
Definition: FUGen.hh:54
ProGe::IGenerationPhases::build
virtual void build()=0
ProGe::HDL
HDL
HDLs supported by ProGe.
Definition: ProGeTypes.hh:40