OpenASIP
2.0
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This is the complete list of members for AlteraOnchipRamGenerator, including all inherited members.
addGenerics(ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex) | AlteraMemGenerator | protectedvirtual |
addLsu(TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts) | MemoryGenerator | |
addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId) | AlteraMemGenerator | virtual |
addParameter(const ProGe::Parameter &add) | MemoryGenerator | protected |
addPort(const TCEString &name, HDLPort *port) | MemoryGenerator | protected |
ADDRW_G | AlteraMemGenerator | protectedstatic |
addrWidth_ | MemoryGenerator | private |
AlteraMemGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream) | AlteraMemGenerator | |
AlteraOnchipRamGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream) | AlteraOnchipRamGenerator | |
BlockPair typedef | MemoryGenerator | protected |
checkFuPort(const std::string fuPort, std::vector< TCEString > &reasons) const | MemoryGenerator | protectedvirtual |
CLOCK_PORT | MemoryGenerator | privatestatic |
COMPONENT_FILE | AlteraOnchipRamGenerator | privatestatic |
connectPorts(ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId) | MemoryGenerator | protectedvirtual |
corePortName(const TCEString &portBaseName, int coreId) const | MemoryGenerator | protected |
createMemoryNetlistBlock(ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId) | MemoryGenerator | protectedvirtual |
DATAW_G | AlteraMemGenerator | protectedstatic |
DEV_FAMILY_G | AlteraMemGenerator | protectedstatic |
errorStream() | MemoryGenerator | protected |
errorStream_ | MemoryGenerator | private |
generateComponentFile(TCEString outputPath) | AlteraOnchipRamGenerator | virtual |
generatesComponentHdlFile() const | AlteraOnchipRamGenerator | virtual |
hasLSUArchitecture() const | MemoryGenerator | protected |
INIT_FILE_G | AlteraMemGenerator | protectedstatic |
initFile_ | MemoryGenerator | private |
initializationFile() const | MemoryGenerator | |
instanceName(int coreId, int memIndex) const | AlteraOnchipRamGenerator | protectedvirtual |
instantiateAlteraTemplate(const TCEString &templateFile, const TCEString &outputPath) const | AlteraMemGenerator | protected |
instantiateTemplate(const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const | MemoryGenerator | protected |
integrator_ | MemoryGenerator | private |
isCompatible(const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const | MemoryGenerator | virtual |
lsuArch_ | MemoryGenerator | private |
lsuArchitecture() const | MemoryGenerator | protected |
lsuPorts_ | MemoryGenerator | private |
mauWidth_ | MemoryGenerator | private |
memoryAddrWidth() const | MemoryGenerator | |
MemoryGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream) | MemoryGenerator | |
memoryIndexString(int coreId, int memIndex) const | MemoryGenerator | protected |
memoryMauSize() const | MemoryGenerator | |
memoryTotalWidth() const | MemoryGenerator | |
memoryWidthInMaus() const | MemoryGenerator | |
memPorts_ | MemoryGenerator | private |
moduleName() const | AlteraOnchipRamGenerator | protectedvirtual |
parameter(int index) const | MemoryGenerator | protected |
parameterCount() const | MemoryGenerator | protected |
ParameterList typedef | MemoryGenerator | private |
params_ | MemoryGenerator | private |
platformIntegrator() const | MemoryGenerator | protected |
port(int index) const | MemoryGenerator | protected |
portByKeyName(TCEString name) const | MemoryGenerator | protected |
portCount() const | MemoryGenerator | protected |
portKeyName(const HDLPort *port) const | MemoryGenerator | protected |
PortMap typedef | MemoryGenerator | protected |
RESET_PORT | MemoryGenerator | privatestatic |
templatePath() const | MemoryGenerator | protected |
ttaCoreName() const | MemoryGenerator | protected |
warningStream() | MemoryGenerator | protected |
warningStream_ | MemoryGenerator | private |
widthInMaus_ | MemoryGenerator | private |
~AlteraMemGenerator() | AlteraMemGenerator | virtual |
~AlteraOnchipRamGenerator() | AlteraOnchipRamGenerator | virtual |
~MemoryGenerator() | MemoryGenerator | virtual |