AlteraOnchipRamGenerator Class Reference

#include <AlteraOnchipRamGenerator.hh>

Inheritance diagram for AlteraOnchipRamGenerator:

Collaboration diagram for AlteraOnchipRamGenerator:

Public Member Functions
	AlteraOnchipRamGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
virtual	~AlteraOnchipRamGenerator ()
virtual bool	generatesComponentHdlFile () const
virtual std::vector< TCEString >	generateComponentFile (TCEString outputPath)
Public Member Functions inherited from AlteraMemGenerator
	AlteraMemGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
virtual	~AlteraMemGenerator ()
virtual void	addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
Public Member Functions inherited from MemoryGenerator
	MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
virtual	~MemoryGenerator ()
virtual bool	isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const
int	memoryTotalWidth () const
int	memoryMauSize () const
int	memoryWidthInMaus () const
int	memoryAddrWidth () const
TCEString	initializationFile () const
void	addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

Protected Member Functions
virtual TCEString	moduleName () const
virtual TCEString	instanceName (int coreId, int memIndex) const
Protected Member Functions inherited from AlteraMemGenerator
std::vector< TCEString >	instantiateAlteraTemplate (const TCEString &templateFile, const TCEString &outputPath) const
virtual void	addGenerics (ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex)
Protected Member Functions inherited from MemoryGenerator
virtual bool	checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const
virtual void	connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
virtual MemoryGenerator::BlockPair	createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
const PlatformIntegrator *	platformIntegrator () const
std::ostream &	warningStream ()
std::ostream &	errorStream ()
int	portCount () const
const HDLPort *	port (int index) const
const HDLPort *	portByKeyName (TCEString name) const
TCEString	portKeyName (const HDLPort *port) const
void	addPort (const TCEString &name, HDLPort *port)
int	parameterCount () const
const ProGe::Parameter &	parameter (int index) const
void	addParameter (const ProGe::Parameter &add)
TCEString	ttaCoreName () const
TCEString	memoryIndexString (int coreId, int memIndex) const
TCEString	templatePath () const
void	instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const
bool	hasLSUArchitecture () const
const TTAMachine::FunctionUnit &	lsuArchitecture () const
TCEString	corePortName (const TCEString &portBaseName, int coreId) const

Static Private Attributes
static const TCEString	COMPONENT_FILE

Additional Inherited Members
Protected Types inherited from MemoryGenerator
typedef std::multimap< TCEString, HDLPort * >	PortMap
typedef std::pair< ProGe::NetlistBlock *, ProGe::VirtualNetlistBlock * >	BlockPair
Static Protected Attributes inherited from AlteraMemGenerator
static const TCEString	INIT_FILE_G = "init_file_g"
static const TCEString	DEV_FAMILY_G = "dev_family_g"
static const TCEString	ADDRW_G = "addrw_g"
static const TCEString	DATAW_G = "dataw_g"

Detailed Description

Definition at line 43 of file AlteraOnchipRamGenerator.hh.

Constructor & Destructor Documentation

AlteraOnchipRamGenerator()

AlteraOnchipRamGenerator::AlteraOnchipRamGenerator	(	int	memMauWidth,
		int	widthInMaus,
		int	addrWidth,
		TCEString	initFile,
		const PlatformIntegrator *	integrator,
		std::ostream &	warningStream,
		std::ostream &	errorStream
	)

Definition at line 43 of file AlteraOnchipRamGenerator.cc.

                            : 
    AlteraMemGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
                       integrator, warningStream, errorStream) {
    
    bool inverted = true;
    bool noInvert = false;
    TCEString byteEnableWidth;
    byteEnableWidth << DATAW_G << "/8";
    addPort("dmem_data_in", 
        new HDLPort("q", DATAW_G,
            ProGe::BIT_VECTOR, ProGe::OUT, noInvert,
            memoryTotalWidth()));
    addPort("dmem_data_out",
        new HDLPort("data", DATAW_G,
            ProGe::BIT_VECTOR, ProGe::IN, noInvert,
            memoryTotalWidth()));
    addPort("dmem_addr",
        new HDLPort("address", ADDRW_G,
            ProGe::BIT_VECTOR, ProGe::IN, noInvert,
            memoryAddrWidth()));
    addPort("dmem_mem_en_x",
        new HDLPort("clken", "1", ProGe::BIT, ProGe::IN, inverted, 1));
    addPort("dmem_wr_en_x",
        new HDLPort("wren", "1", ProGe::BIT, ProGe::IN, inverted, 1));
    addPort("dmem_bytemask",
        new HDLPort("byteena", byteEnableWidth, ProGe::BIT_VECTOR,
            ProGe::IN, noInvert, memoryWidthInMaus()));
    addPort("clk",
        new HDLPort("clock", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
}

References MemoryGenerator::addPort(), AlteraMemGenerator::ADDRW_G, ProGe::BIT, ProGe::BIT_VECTOR, AlteraMemGenerator::DATAW_G, ProGe::IN, MemoryGenerator::memoryAddrWidth(), MemoryGenerator::memoryTotalWidth(), MemoryGenerator::memoryWidthInMaus(), and ProGe::OUT.

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~AlteraOnchipRamGenerator()

AlteraOnchipRamGenerator::~AlteraOnchipRamGenerator ( )

virtual

Definition at line 81 of file AlteraOnchipRamGenerator.cc.

                                                    {
}

Member Function Documentation

generateComponentFile()

std::vector< TCEString > AlteraOnchipRamGenerator::generateComponentFile ( TCEString  outputPath )

virtual

Implements MemoryGenerator.

Definition at line 91 of file AlteraOnchipRamGenerator.cc.

                                                                    {
 
    return instantiateAlteraTemplate(COMPONENT_FILE, outputPath);
}

References COMPONENT_FILE, and AlteraMemGenerator::instantiateAlteraTemplate().

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generatesComponentHdlFile()

bool AlteraOnchipRamGenerator::generatesComponentHdlFile ( ) const

virtual

Implements MemoryGenerator.

Definition at line 85 of file AlteraOnchipRamGenerator.cc.

                                                          {
    return true;
}

instanceName()

TCEString AlteraOnchipRamGenerator::instanceName ( int  coreId, int  memIndex  ) const

protectedvirtual

Implements MemoryGenerator.

Definition at line 105 of file AlteraOnchipRamGenerator.cc.

                                                                     {
    
    TCEString iname("onchip_dmem_");
    return iname << memoryIndexString(coreId, memIndex);
}

References MemoryGenerator::memoryIndexString().

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moduleName()

TCEString AlteraOnchipRamGenerator::moduleName ( ) const

protectedvirtual

Implements MemoryGenerator.

Definition at line 98 of file AlteraOnchipRamGenerator.cc.

                                           {
 
    return ttaCoreName() + "_altera_onchip_ram_comp";
}

References MemoryGenerator::ttaCoreName().

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Member Data Documentation

COMPONENT_FILE

const TCEString AlteraOnchipRamGenerator::COMPONENT_FILE

staticprivate

Initial value:

= 
    "altera_onchip_ram_comp.vhd"

Definition at line 70 of file AlteraOnchipRamGenerator.hh.

Referenced by generateComponentFile().

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The documentation for this class was generated from the following files:

• AlteraOnchipRamGenerator.hh
• AlteraOnchipRamGenerator.cc