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Processor Designer (ProDe) is a graphical application mainly for viewing, editing and printing processor architecture definition files. It also allows selecting implementation for each component of the processor, and generating the HDL implementation of the processor. The application is very easy to use and intuitive, thus this section provides help only for the most common problematic situations encountered while using the toolset.
Input: ADF
Output: ADF, VHDL
The main difficulty in using the tool is to understand what is being designed, that is, the limitations placed by the processor template. Details of the processor template are described in [CSJ04].
Processor Desinger can simply be executed from command line with:
prode
The most complex part of ProDe is the operation property dialog which pops up when editing the operations inside a function unit.
The upper right side of the dialog contains the function unit resource table. The resource table is used to describe the pipeline resource usage of the operation inside the function unit. When the function unit is fully pipelined, there are no limitations on executing of successive instructions, thus it should be empty in that case.
If there is some limitation, for example pipeline component, which is used in some clock cycles of the operation execution, so that it limits the execution of successive operations, one ore more pipeline resources should be added to model this component. Each operation that uses the resources (that can be arbitrarily named), should include timing information by marking the clock cycles the resource is used from the start of the operation.
For example, in a multiplication function unit, which has a 4-cycle latency, and is not pipelined at all; the resource called, for example, ``multiplier'' should be created, by pressing the add button. All the operations which use the multiplier component should have the first 4 clock cycles marked to use this resource in the resource usage table. Pressing the ``add'' button adds row to the resource usage table.
The lower right side of the dialog contains the operand I/O timing information. This describes when the operands are read or written from/to the function unit ports. R letter here means reading an input operand and W means writing a result to an output operand.
Note: the instruction scheduler of TCE cannot yet take advantage of scheduling input operands after the triggering operand, so all the input operands should be read at cycle 0.
The writes of the results effectively mark the latency of the operation. Important: The cycles from this table for the result writes start one cycle after the trigger of the operand. So write in cycle 0 means that the result is ready on the cycle following the triggering of the operation, not the same cycle as the trigger is executed.
If an operation produces multiple results, they can be written at different clock cycles.