8 Hardware Database Editor (HDB Editor)

HDB Editor (hdbeditor) is a graphical frontend for creating and modifying Hardware Databases i.e. HDB files (see Section 2.2.3 for details). By default, all the example HDB files are stored in the directory hdb/ of the TCE installation directory.

1 Usage

This section is intended to familiarize the reader to basic usage of the HDB Editor.

HDB editor can be launched from command line by entering:

hdbeditor

You can also give a .hdb-file as parameter for the hdbeditor:

hdbeditor customHardware.hdb

1 Creating a new HDB file

Choose ``File'' | ``Create HDB...''. From there, type a name for your .hdb file and save it in the default HDB path (tce/hdb).

After that, you can start adding new TTA components such as function units, register files, buses and sockets from ``Edit'' | ``Add''.

2 Adding new components

A new function unit's architecture can only be added through an existing ADF file unlike register files, which can only be added by hand. The ADF files can be done in the ProDe tool. After adding a new architecture, one can add an implementation for it by right-clicking on it and choosing ``Add implementation''

The architecture implementation can be given either by hand or by a VHDL file.

After setting up the architecture, one can add new entries (function units, register files, buses, sockets) for the architectures.

3 Adding FU/RF HDL source files

HDL files of Function Unit and Register File implementations must be added in right compilation order i.e. the source file which needs to be compiled first is first in the list and so on.

Figure 4.8: HDB Editor Main window.

4 Using SRAM based Register File Implementations

Register files of TTA machines may be implemented using synchronous SRAM memory blocks. To support SRAM memory based register files the requirements are:

1. SRAM memory blocks have fixed latency of one for read operation.
2. SRAM memory blocks can handle as many writes and reads in a single clock cycle as specified in the ADF.
3. TCE's Default IC / Decoder Plugin is used to generate the decoder of the processor.
4. SRAM bypasses write data to reading port if the accesses occurs at same cycle and at same address. Alternatively, the SRAM is wrapped in a module with the bypass logic.

To enable SRAM based register files in the implementation TCE must be notified if a implementation of RF requires separate address cycle. This is done in HDBEditor by setting option ``Separate address cycle'' to true in the Register File Implementation dialog. This option adjusts the timing of read accesses to be a cycle earlier. The option is effective only if default IC / Decoder Plugin (see: 4.5.1) is used to generate the machine since it does necessary modification to the instruction pipeline to tweak timings.

HDB includes a single SRAM register file implementation using dual-port block RAM inferred by Xilinx XST synthesis tool.