OpenASIP 2.2
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AvalonIntegrator.cc
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1/*
2 Copyright (c) 2002-2010 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file AvalonIntegrator.cc
26 *
27 * Implementation of AvalonIntegrator class.
28 *
29 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30 * @note rating: red
31 */
32
33#include "AvalonIntegrator.hh"
34#include "MemoryGenerator.hh"
36using std::endl;
37
39
41 AlteraIntegrator(), sopcGenerator_(NULL) {
42}
43
47 ProGe::HDL hdl,
48 TCEString progeOutputDir,
49 TCEString coreEntityName,
50 TCEString outputDir,
51 TCEString programName,
52 int targetClockFreq,
53 std::ostream& warningStream,
54 std::ostream& errorStream,
55 const MemInfo& imem,
56 MemType dmemType):
57 AlteraIntegrator(machine, idf, hdl, progeOutputDir, coreEntityName,
58 outputDir, programName, targetClockFreq, warningStream,
59 errorStream, imem, dmemType),
60 sopcGenerator_(new SOPCBuilderFileGenerator(coreEntityName, this)),
61 deviceFamily_(DEFAULT_DEVICE_FAMILY_) {
62}
63
64
66
67 if (sopcGenerator_ != NULL) {
68 delete sopcGenerator_;
69 }
70}
71
72void
73AvalonIntegrator::printInfo(std::ostream& stream) const {
74
75 stream
76 << "Integrator name: AvalonIntegrator" << endl
77 << "---------------------------------" << endl
78 << "Creates a SOPC Builder component from TTA core." << endl
79 << "Processor must have avalon_lsu or avalon_sfu (from avalon.hdb) "
80 << "for correct behaviour." << endl
81 << "Supported instruction memory types are 'onchip' and 'vhdl_array."
82 << endl
83 << "If 'normal' lsu is used, supported data memory type is 'onchip'."
84 << endl
85 << "If avalon_lsu is used, data memory type must be 'none'." << endl
86 << "FPGA device family can be changed. Default device family is "
87 << DEFAULT_DEVICE_FAMILY_ << endl << endl;
88}
89
90
93
94 return "avalon_d";
95}
96
97
98bool
100
101 return false;
102}
103
104
110
111
114
115 return deviceFamily_;
116}
117
118
119void
121
122 deviceFamily_ = devFamily;
123}
124
125
128 return "";
129}
130
133 return "";
134}
135
136int
138 return 1;
139}
TTAMachine::Machine * machine
the architecture definition of the estimated processor
virtual void printInfo(std::ostream &stream) const
virtual TCEString devicePackage() const
virtual void setDeviceFamily(TCEString devFamily)
static const TCEString DEFAULT_DEVICE_FAMILY_
virtual ~AvalonIntegrator()
virtual int targetClockFrequency() const
virtual TCEString pinTag() const
virtual TCEString deviceFamily() const
virtual bool chopTaggedSignals() const
ProjectFileGenerator * sopcGenerator_
virtual ProjectFileGenerator * projectFileGenerator() const
virtual TCEString deviceSpeedClass() const
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40