OpenASIP 2.2
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Public Member Functions | Private Attributes | List of all members
HDLGenerator::Register Class Reference

#include <HDLRegister.hh>

Collaboration diagram for HDLGenerator::Register:
Collaboration graph

Public Member Functions

 Register (std::string name, int width, WireType wt, ResetOption rst=ResetOption::Mandatory)
 
 Register (std::string name, int width=1, ResetOption rst=ResetOption::Mandatory)
 
 Register (std::string name, std::string width, ResetOption rst=ResetOption::Mandatory)
 
Width width () noexcept
 
std::string name ()
 
RegistersetResetValue (BinaryLiteral &&rhs)
 
void reset (std::ostream &stream, Language lang, int ident)
 
void declare (std::ostream &stream, Language lang, int ident)
 
ResetOption resetOption () const noexcept
 

Private Attributes

std::string name_
 
std::string strWidth_
 
int width_
 
WireType wt_
 
ResetOption rst_
 
BinaryLiteral literal_
 

Detailed Description

Sync signal/sync reg.

Definition at line 51 of file HDLRegister.hh.

Constructor & Destructor Documentation

◆ Register() [1/3]

HDLGenerator::Register::Register ( std::string  name,
int  width,
WireType  wt,
ResetOption  rst = ResetOption::Mandatory 
)
inline

Definition at line 53 of file HDLRegister.hh.

◆ Register() [2/3]

HDLGenerator::Register::Register ( std::string  name,
int  width = 1,
ResetOption  rst = ResetOption::Mandatory 
)
inline

Definition at line 57 of file HDLRegister.hh.

◆ Register() [3/3]

HDLGenerator::Register::Register ( std::string  name,
std::string  width,
ResetOption  rst = ResetOption::Mandatory 
)
inline

Definition at line 61 of file HDLRegister.hh.

64 wt_(WireType::Auto), rst_(rst), literal_("") {}

Member Function Documentation

◆ declare()

void HDLGenerator::Register::declare ( std::ostream &  stream,
Language  lang,
int  ident 
)
inline

Definition at line 100 of file HDLRegister.hh.

100 {
101 if (lang == Language::VHDL) {
102 stream << StringTools::indent(ident) << "signal "
103 << name() << " : ";
104 if (width_ < 0 || width_ > 1 || wt_ == WireType::Vector) {
105 if (strWidth_.empty()) {
106 stream << "std_logic_vector("
107 << std::to_string(width_ - 1)
108 << " downto 0);\n";
109 } else {
110 stream << "std_logic_vector(" << strWidth_
111 << "-1 downto 0);\n";
112 }
113 } else {
114 stream << "std_logic;\n";
115 }
116 } else if (lang == Language::Verilog) {
117 stream << StringTools::indent(ident) << "reg ";
118 if (width_ < 0 || width_ > 1) {
119 if (strWidth_.empty()) {
120 stream << "[" << std::to_string(width_ - 1) << ":0] ";
121 } else {
122 stream << "[" << strWidth_ << "-1:0] ";
123 }
124 }
125 stream << name() << ";\n";
126 } else {
127 throw std::runtime_error(__PRETTY_FUNCTION__);
128 }
129 }
static std::string indent(int level)

References StringTools::indent(), name(), strWidth_, HDLGenerator::Vector, HDLGenerator::Verilog, HDLGenerator::VHDL, width_, and wt_.

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◆ name()

std::string HDLGenerator::Register::name ( )
inline

Definition at line 68 of file HDLRegister.hh.

68{ return name_; }

References name_.

Referenced by declare(), and reset().

◆ reset()

void HDLGenerator::Register::reset ( std::ostream &  stream,
Language  lang,
int  ident 
)
inline

Definition at line 75 of file HDLRegister.hh.

75 {
76 stream << StringTools::indent(ident) << name() << " <= ";
77 if (lang == Language::VHDL) {
78 if (literal_.name().empty()) {
79 if (width_ == 1 && wt_ != WireType::Vector) {
80 stream << "'0';\n";
81 } else {
82 stream << "(others => '0');\n";
83 }
84 } else {
85 literal_.hdl(stream, lang);
86 stream << ";\n";
87 }
88 } else if (lang == Language::Verilog) {
89 if (literal_.name().empty()) {
90 stream << "0;\n";
91 } else {
92 literal_.hdl(stream, lang);
93 stream << ";\n";
94 }
95 } else {
96 throw std::runtime_error(__PRETTY_FUNCTION__);
97 }
98 }
void hdl(std::ostream &stream, Language lang, int level)
Definition LHSValue.cc:37

References HDLGenerator::LHSValue::hdl(), StringTools::indent(), literal_, name(), HDLGenerator::BinaryLiteral::name(), HDLGenerator::Vector, HDLGenerator::Verilog, HDLGenerator::VHDL, width_, and wt_.

Referenced by HDLGenerator::Synchronous::hdl(), and HDLGenerator::Synchronous::vhdlReset().

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◆ resetOption()

ResetOption HDLGenerator::Register::resetOption ( ) const
inlinenoexcept

Definition at line 131 of file HDLRegister.hh.

131{ return rst_; }

References rst_.

Referenced by HDLGenerator::Synchronous::hdl(), and HDLGenerator::Synchronous::vhdlReset().

◆ setResetValue()

Register & HDLGenerator::Register::setResetValue ( BinaryLiteral &&  rhs)
inline

Definition at line 70 of file HDLRegister.hh.

70 {
71 literal_ = rhs;
72 return *this;
73 }

References literal_.

◆ width()

Width HDLGenerator::Register::width ( )
inlinenoexcept

Definition at line 66 of file HDLRegister.hh.

66{ return {strWidth_, width_}; }

References strWidth_, and width_.

Member Data Documentation

◆ literal_

BinaryLiteral HDLGenerator::Register::literal_
private

Definition at line 139 of file HDLRegister.hh.

Referenced by reset(), and setResetValue().

◆ name_

std::string HDLGenerator::Register::name_
private

Definition at line 134 of file HDLRegister.hh.

Referenced by name().

◆ rst_

ResetOption HDLGenerator::Register::rst_
private

Definition at line 138 of file HDLRegister.hh.

Referenced by resetOption().

◆ strWidth_

std::string HDLGenerator::Register::strWidth_
private

Definition at line 135 of file HDLRegister.hh.

Referenced by declare(), and width().

◆ width_

int HDLGenerator::Register::width_
private

Definition at line 136 of file HDLRegister.hh.

Referenced by declare(), reset(), and width().

◆ wt_

WireType HDLGenerator::Register::wt_
private

Definition at line 137 of file HDLRegister.hh.

Referenced by declare(), and reset().


The documentation for this class was generated from the following file: