OpenASIP 2.2
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HDLRegister.hh
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1/*
2 Copyright (c) 2018 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25* @file HDLGenerator.hh
26*
27* @author Aleksi Tervo 2018 (aleksi.tervo-no.spam-tut.fi)
28*/
29#pragma once
30#include "HWGenTools.hh"
31#include "LHSValue.hh"
32#include "StringTools.hh"
33#include <boost/format.hpp>
34#include <chrono>
35#include <cmath>
36#include <ctime>
37#include <deque>
38#include <iomanip>
39#include <iostream>
40#include <memory>
41#include <sstream>
42#include <string>
43#include <unordered_map>
44#include <unordered_set>
45#include <vector>
46
47namespace HDLGenerator {
48 /**
49 * Sync signal/sync reg.
50 */
51 class Register {
52 public:
53 Register(std::string name, int width, WireType wt,
55 : name_(name), strWidth_(), width_(width), wt_(wt),
56 rst_(rst), literal_("") {}
57 Register(std::string name, int width = 1,
60 wt_(WireType::Auto), rst_(rst), literal_("") {}
61 Register(std::string name, std::string width,
64 wt_(WireType::Auto), rst_(rst), literal_("") {}
65
66 Width width() noexcept { return {strWidth_, width_}; }
67
68 std::string name() { return name_; }
69
71 literal_ = rhs;
72 return *this;
73 }
74
75 void reset(std::ostream& stream, Language lang, int ident) {
76 stream << StringTools::indent(ident) << name() << " <= ";
77 if (lang == Language::VHDL) {
78 if (literal_.name().empty()) {
79 if (width_ == 1 && wt_ != WireType::Vector) {
80 stream << "'0';\n";
81 } else {
82 stream << "(others => '0');\n";
83 }
84 } else {
85 literal_.hdl(stream, lang);
86 stream << ";\n";
87 }
88 } else if (lang == Language::Verilog) {
89 if (literal_.name().empty()) {
90 stream << "0;\n";
91 } else {
92 literal_.hdl(stream, lang);
93 stream << ";\n";
94 }
95 } else {
96 throw std::runtime_error(__PRETTY_FUNCTION__);
97 }
98 }
99
100 void declare(std::ostream& stream, Language lang, int ident) {
101 if (lang == Language::VHDL) {
102 stream << StringTools::indent(ident) << "signal "
103 << name() << " : ";
104 if (width_ < 0 || width_ > 1 || wt_ == WireType::Vector) {
105 if (strWidth_.empty()) {
106 stream << "std_logic_vector("
107 << std::to_string(width_ - 1)
108 << " downto 0);\n";
109 } else {
110 stream << "std_logic_vector(" << strWidth_
111 << "-1 downto 0);\n";
112 }
113 } else {
114 stream << "std_logic;\n";
115 }
116 } else if (lang == Language::Verilog) {
117 stream << StringTools::indent(ident) << "reg ";
118 if (width_ < 0 || width_ > 1) {
119 if (strWidth_.empty()) {
120 stream << "[" << std::to_string(width_ - 1) << ":0] ";
121 } else {
122 stream << "[" << strWidth_ << "-1:0] ";
123 }
124 }
125 stream << name() << ";\n";
126 } else {
127 throw std::runtime_error(__PRETTY_FUNCTION__);
128 }
129 }
130
131 ResetOption resetOption() const noexcept { return rst_; }
132
133 private:
134 std::string name_;
135 std::string strWidth_;
140 };
141}
void hdl(std::ostream &stream, Language lang, int level)
Definition LHSValue.cc:37
Register(std::string name, std::string width, ResetOption rst=ResetOption::Mandatory)
void reset(std::ostream &stream, Language lang, int ident)
Register(std::string name, int width=1, ResetOption rst=ResetOption::Mandatory)
Register(std::string name, int width, WireType wt, ResetOption rst=ResetOption::Mandatory)
ResetOption resetOption() const noexcept
void declare(std::ostream &stream, Language lang, int ident)
Width width() noexcept
Register & setResetValue(BinaryLiteral &&rhs)
static std::string indent(int level)