OpenASIP 2.2
Loading...
Searching...
No Matches
Public Member Functions | Protected Member Functions | List of all members
OTASimulationController Class Reference

#include <OTASimulationController.hh>

Inheritance diagram for OTASimulationController:
Inheritance graph
Collaboration diagram for OTASimulationController:
Collaboration graph

Public Member Functions

 OTASimulationController (SimulatorFrontend &frontend, const TTAMachine::Machine &machine, const TTAProgram::Program &program)
 
virtual ~OTASimulationController ()
 
- Public Member Functions inherited from SimulationController
 SimulationController (SimulatorFrontend &frontend, const TTAMachine::Machine &machine, const TTAProgram::Program &program, bool fuResourceConflictDetection=true, bool detailedSimulation=false)
 
virtual ~SimulationController ()
 
virtual void step (double count=1)
 
virtual void next (int count=1)
 
virtual void run ()
 
virtual void runUntil (UIntWord address)
 
virtual void reset ()
 
virtual InstructionAddress programCounter () const
 
virtual MachineStatemachineState (int core=-1)
 
virtual const InstructionMemoryinstructionMemory (int core=-1) const
 
virtual std::string registerFileValue (const std::string &rfName, int registerIndex=-1)
 
virtual SimValue immediateUnitRegisterValue (const std::string &iuName, int index=-1)
 
virtual SimValue FUPortValue (const std::string &fuName, const std::string &portName)
 
- Public Member Functions inherited from TTASimulationController
 TTASimulationController (SimulatorFrontend &frontend, const TTAMachine::Machine &machine, const TTAProgram::Program &program)
 
virtual ~TTASimulationController ()
 
virtual void prepareToStop (StopReason reason)
 
virtual unsigned int stopReasonCount () const
 
virtual StopReason stopReason (unsigned int index) const
 
virtual SimulationStatus state () const
 
virtual InstructionAddress lastExecutedInstruction (int coreId=-1) const
 
virtual ClockCycleCount clockCount () const
 
virtual MemorySystemmemorySystem (int coreId=-1)
 
virtual SimulatorFrontendfrontend ()
 
virtual bool automaticFinishImpossible () const
 
virtual std::set< InstructionAddressfindProgramExitPoints (const TTAProgram::Program &program, const TTAMachine::Machine &machine) const
 

Protected Member Functions

void advanceMachineCycle (unsigned pcAdd)
 
virtual bool simulateCycle ()
 
- Protected Member Functions inherited from TTASimulationController
 TTASimulationController (const TTASimulationController &)
 Copying not allowed.
 
TTASimulationControlleroperator= (const TTASimulationController &)
 Assignment not allowed.
 

Additional Inherited Members

- Public Types inherited from TTASimulationController
enum  SimulationStatus {
  STA_INITIALIZING , STA_INITIALIZED , STA_RUNNING , STA_STOPPED ,
  STA_FINISHED
}
 The states of simulation. More...
 
- Protected Types inherited from SimulationController
typedef std::vector< MachineState * > MachineStateContainer
 
- Protected Types inherited from TTASimulationController
typedef std::set< StopReasonStopReasonContainer
 The container type for reasons why simulation stop was requested.
 
- Protected Attributes inherited from SimulationController
MachineStateContainer machineStates_
 The machine state models for the simulated cores.
 
std::vector< InstructionMemory * > instructionMemories_
 The instruction memory models of cores.
 
- Protected Attributes inherited from TTASimulationController
SimulatorFrontendfrontend_
 Reference to the simulator frontend.
 
const TTAMachine::MachinesourceMachine_
 The simulated Machine Object Model.
 
const TTAProgram::Programprogram_
 Program object model of the simulated program.
 
bool stopRequested_
 Flag indicating that simulation should stop.
 
StopReasonContainer stopReasons_
 The set of reasons the simulation was stopped.
 
SimulationStatus state_
 The current state of the simulation.
 
ClockCycleCount clockCount_
 How many clock cycles have been simulated.
 
std::vector< InstructionAddresslastExecutedInstruction_
 The address of the last executed instruction.
 
InstructionAddress initialPC_
 The address of the first executed instruction.
 
bool automaticFinishImpossible_
 If this is true, simulation cannot be finished automatically.
 
InstructionAddress firstIllegalInstructionIndex_
 The index of the first illegal instruction in the instruction sequence.
 

Detailed Description

Definition at line 40 of file OTASimulationController.hh.

Constructor & Destructor Documentation

◆ OTASimulationController()

OTASimulationController::OTASimulationController ( SimulatorFrontend frontend,
const TTAMachine::Machine machine,
const TTAProgram::Program program 
)

Definition at line 40 of file OTASimulationController.cc.

43 :
45}
TTAMachine::Machine * machine
the architecture definition of the estimated processor
find Finds info of the inner loops in the program
virtual SimulatorFrontend & frontend()

◆ ~OTASimulationController()

OTASimulationController::~OTASimulationController ( )
virtual

Definition at line 47 of file OTASimulationController.cc.

47 {
48}

Member Function Documentation

◆ advanceMachineCycle()

void OTASimulationController::advanceMachineCycle ( unsigned  pcAdd)
protected

Definition at line 52 of file OTASimulationController.cc.

52 {
53
54 const unsigned int core = 0;
56 //InstructionMemory& imem = *instructionMemories_[core];
59
61
62 if (!gcu.isIdle()) {
63 gcu.endClock();
64 }
65
69
70 gcu.programCounter() += pcAdd;
71 if (!gcu.isIdle())
72 gcu.advanceClock();
73
75}
virtual void endClock()
Definition FUState.cc:122
bool isIdle()
virtual void advanceClock()
Definition GCUState.cc:98
InstructionAddress & programCounter()
void endClockOfAllFUStates()
void advanceClockOfAllFUStates()
void advanceClockOfAllGuardStates()
GCUState & gcuState()
void advanceClockOfSharedMemories()
void advanceClockOfLocalMemories()
MachineStateContainer machineStates_
The machine state models for the simulated cores.
virtual MachineState & machineState(int core=-1)
MemorySystem & memorySystem(int coreId=-1)
SimulatorFrontend & frontend_
Reference to the simulator frontend.
virtual MemorySystem & memorySystem(int coreId=-1)

References GCUState::advanceClock(), MachineState::advanceClockOfAllFUStates(), MachineState::advanceClockOfAllGuardStates(), MemorySystem::advanceClockOfLocalMemories(), MemorySystem::advanceClockOfSharedMemories(), FUState::endClock(), MachineState::endClockOfAllFUStates(), TTASimulationController::frontend_, MachineState::gcuState(), FUState::isIdle(), SimulationController::machineState(), SimulationController::machineStates_, SimulatorFrontend::memorySystem(), TTASimulationController::memorySystem(), and GCUState::programCounter().

Referenced by simulateCycle().

Here is the call graph for this function:

◆ simulateCycle()

bool OTASimulationController::simulateCycle ( )
protectedvirtual

Simulates an instruction cycle, both its explicit and implicit instructions.

Reimplemented from SimulationController.

Definition at line 81 of file OTASimulationController.cc.

81 {
82
83 std::vector<InstructionAddress> lastExecutedInstructions =
85
86 bool finished = false;
87
88 int finishedCoreCount = 0;
89
90 const unsigned int core = 0;
94 const InstructionAddress pc = gcu.programCounter();
95
96 try {
98
99 bool exitPoint = false;
100 if (imem.hasInstructionAt(pc)) {
101 ExecutableInstruction& instruction = imem.instructionAt(pc);
102 instruction.execute();
103
104 lastExecutedInstructions[core] = pc;
105
107
108 if (imem.hasImplicitInstructionsAt(pc)) {
109 const auto& implInstructions = imem.implicitInstructionsAt(pc);
110 for (size_t i = 0; i < implInstructions.size(); ++i) {
111 ExecutableInstruction& implInstruction =
112 *implInstructions.at(i);
113 implInstruction.execute();
114 exitPoint |= implInstruction.isExitPoint();
116 }
117 }
118
119 exitPoint |= instruction.isExitPoint();
120 }
121
122 // check if the instruction was a return point from the program or
123 // the next executed instruction would be sequentially over the
124 // instruction space (PC+1 would overflow out of the program)
125 if (exitPoint ||
128 ++finishedCoreCount;
129 }
130 } catch (const Exception& e) {
133 e.errorMessage());
135 return false;
136 }
137
138 if (finishedCoreCount > 0)
139 finished = true;
140
142
143 lastExecutedInstruction_ = lastExecutedInstructions;
144
145 // this is the instruction count in case of OTA
146 ++clockCount_;
147
148 if (finished) {
150 stopRequested_ = true;
151 return false;
152 }
153
156 return true;
157}
UInt32 InstructionAddress
Definition BaseType.hh:175
@ SRE_RUNTIME_ERROR
A fatal runtime error occured in the simulated program.
std::string errorMessage() const
Definition Exception.cc:123
bool isExitPoint() const
void handleEvent(int event)
ExecutableInstruction & instructionAt(InstructionAddress address)
const InstructionContainer & implicitInstructionsAt(InstructionAddress addr) const
bool hasInstructionAt(InstructionAddress addr) const
bool hasImplicitInstructionsAt(InstructionAddress addr) const
void clearBuses()
void setFinished(bool finished=true)
void advanceMachineCycle(unsigned pcAdd)
std::vector< InstructionMemory * > instructionMemories_
The instruction memory models of cores.
@ SE_NEW_INSTRUCTION
Generated before executing a new instructon.
@ SE_CYCLE_END
Generated before advancing the simulator clock at the end of a simulation cycle.
SimulationEventHandler & eventHandler()
void reportSimulatedProgramError(RuntimeErrorSeverity severity, const std::string &description)
@ RES_FATAL
Fatal runtime error, there is a serious error in the simulated program, thus it makes no sense to go ...
std::vector< InstructionAddress > lastExecutedInstruction_
The address of the last executed instruction.
bool stopRequested_
Flag indicating that simulation should stop.
virtual void prepareToStop(StopReason reason)
@ STA_FINISHED
Simulation ended after executing the last instruction.
InstructionAddress firstIllegalInstructionIndex_
The index of the first illegal instruction in the instruction sequence.
SimulationStatus state_
The current state of the simulation.
ClockCycleCount clockCount_
How many clock cycles have been simulated.

References advanceMachineCycle(), MachineState::clearBuses(), TTASimulationController::clockCount_, Exception::errorMessage(), SimulatorFrontend::eventHandler(), ExecutableInstruction::execute(), TTASimulationController::firstIllegalInstructionIndex_, TTASimulationController::frontend_, MachineState::gcuState(), Informer::handleEvent(), InstructionMemory::hasImplicitInstructionsAt(), InstructionMemory::hasInstructionAt(), InstructionMemory::implicitInstructionsAt(), InstructionMemory::instructionAt(), SimulationController::instructionMemories_, ExecutableInstruction::isExitPoint(), TTASimulationController::lastExecutedInstruction_, SimulationController::machineState(), SimulationController::machineStates_, TTASimulationController::prepareToStop(), GCUState::programCounter(), SimulatorFrontend::reportSimulatedProgramError(), SimulatorFrontend::RES_FATAL, SimulationEventHandler::SE_CYCLE_END, SimulationEventHandler::SE_NEW_INSTRUCTION, MachineState::setFinished(), SRE_RUNTIME_ERROR, TTASimulationController::STA_FINISHED, TTASimulationController::state_, and TTASimulationController::stopRequested_.

Here is the call graph for this function:

The documentation for this class was generated from the following files: