#include <TCEInstrInfo.hh>

Inheritance diagram for llvm::TCEInstrInfo:

Collaboration diagram for llvm::TCEInstrInfo:

Public Member Functions
	TCEInstrInfo (const TCETargetMachinePlugin *plugin)

virtual	~TCEInstrInfo ()

const InstrItineraryData *	getInstrItineraryData () const

virtual const TargetRegisterInfo &	getRegisterInfo () const

virtual unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

unsigned	removeBranch (MachineBasicBlock &mbb, int *BytesRemoved=nullptr) const override

virtual bool	BlockHasNoFallThrough (const MachineBasicBlock &MBB) const

virtual void	storeRegToStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, unsigned srcReg, bool isKill, int frameIndex, const TargetRegisterClass *rc, Register vReg) const

virtual void	storeRegToStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, Register srcReg, bool isKill, int frameIndex, const TargetRegisterClass rc, const TargetRegisterInfo , Register vReg) const override

virtual void	loadRegFromStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, unsigned destReg, int frameIndex, const TargetRegisterClass *rc, Register vReg) const

virtual void	loadRegFromStackSlot (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, Register destReg, int frameIndex, const TargetRegisterClass rc, const TargetRegisterInfo , Register vReg) const override

virtual void	copyPhysReg (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, const DebugLoc &DL, MCRegister destReg, MCRegister srcReg, bool KillSrc) const override

virtual bool	reverseBranchCondition (llvm::SmallVectorImpl< llvm::MachineOperand > &cond) const override

virtual bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, llvm::SmallVectorImpl< llvm::MachineOperand > &cond, bool allowModify=false) const override

std::unique_ptr< PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
	Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

virtual bool	isPredicated (const MachineInstr &MI) const override

virtual bool	isPredicable (const MachineInstr &MI) const override

virtual bool	PredicateInstruction (MachineInstr &mi, ArrayRef< MachineOperand > cond) const override

virtual bool	ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override

virtual bool	SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override

virtual void	insertCCBranch (MachineBasicBlock &mbb, MachineBasicBlock &tbb, ArrayRef< MachineOperand > cond, const DebugLoc &dl) const

virtual bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

virtual bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override

std::tuple< int, int >	getPointerAdjustment (int offset) const

virtual DFAPacketizer *	CreateTargetScheduleState (const TargetSubtargetInfo &) const override

Private Member Functions
int	getMatchingCondBranchOpcode (int Opc, bool inverted) const

bool	copyPhysVectorReg (MachineBasicBlock &mbb, MachineBasicBlock::iterator mbbi, const DebugLoc &DL, MCRegister destReg, MCRegister srcReg, bool killSrc) const

Private Attributes
InstrItineraryData	InstrItins

const TCERegisterInfo	ri_

const TCETargetMachinePlugin *	plugin_

Detailed Description

!! Important !! ************* ON EVERY LLVM UPDATE CHECK THESE INTERFACES VERY CAREFULLY FROM include/llvm/Target/TargetInstrInfo.h

Compiler doesn warn or give error if parameter lists are changed. Many times also base class implementation works, but does not do very good job.

Definition at line 57 of file TCEInstrInfo.hh.

Constructor & Destructor Documentation

◆ TCEInstrInfo()

TCEInstrInfo::TCEInstrInfo ( const TCETargetMachinePlugin * plugin )

Constructor.

Definition at line 73 of file TCEInstrInfo.cc.

                                          :
    TCEGenInstrInfo(TCE::ADJCALLSTACKDOWN, TCE::ADJCALLSTACKUP),
    ri_(*this), plugin_(plugin) {
}

◆ ~TCEInstrInfo()

TCEInstrInfo::~TCEInstrInfo ( )

virtual

Destructor.

Definition at line 82 of file TCEInstrInfo.cc.

82 {

83}

Member Function Documentation

◆ analyzeBranch()

bool TCEInstrInfo::analyzeBranch	(	MachineBasicBlock &	mbb,
		MachineBasicBlock *&	tbb,
		MachineBasicBlock *&	fbb,
		llvm::SmallVectorImpl< llvm::MachineOperand > &	cond,
		bool	allowModify = `false`
	)		const

overridevirtual

Analyzes branches of MBB.

Parameters

mbb	MBB to analyze
tbb	Puts the jump target or condition true target MBB here
fbb	Puts the condition false target here, if not fall-thru
cond	puts the condition data (predcate reg and T/F) here

Returns: false if could analyze, true if could not analyze

Definition at line 457 of file TCEInstrInfo.cc.

          {
    if (mbb.empty()) {
        return false;
    }
 
    MachineBasicBlock::iterator i = mbb.end(); i--;
 
    MachineInstr& lastIns = *i;
    switch (lastIns.getOpcode()) {
    case TCE::TCEBRCOND:
        tbb = lastIns.getOperand(1).getMBB();
        cond.push_back(i->getOperand(0));
        cond.push_back(MachineOperand::CreateImm(true));
        return false;
    case TCE::TCEBRICOND:
        tbb = lastIns.getOperand(1).getMBB();
        cond.push_back(i->getOperand(0));
        cond.push_back(MachineOperand::CreateImm(false));
        return false;
    case TCE::TCEBRIND:
    case TCE::TCEBR: {
        // indirect jump cannot be analyzed
        if (!lastIns.getOperand(0).isMBB()) {
            return true;
        }
 
        if (i == mbb.begin()) {
            tbb = lastIns.getOperand(0).getMBB();
            return false; // uncond jump only ins in mbb.
        }
        i--;
        if (i->getOpcode() == TCE::TCEBRCOND) {
            tbb = i->getOperand(1).getMBB();
            fbb = lastIns.getOperand(0).getMBB();
            cond.push_back(i->getOperand(0));
            cond.push_back(MachineOperand::CreateImm(true));
            return false;
        }
        if (i->getOpcode() == TCE::TCEBRICOND) {
            tbb = i->getOperand(1).getMBB(); 
            fbb = lastIns.getOperand(0).getMBB();
            cond.push_back(i->getOperand(0));
            cond.push_back(MachineOperand::CreateImm(false));
            return false;
        }
        // two uncond branches not allowed
        assert(i->getOpcode() != TCE::TCEBR);
 
        if (i->getDesc().isBranch()) {
            tbb = i->getOperand(2).getMBB();
            fbb = lastIns.getOperand(0).getMBB();
            return plugin_->analyzeCCBranch(*i, cond);
        } else { // only conditional branch.
            tbb = lastIns.getOperand(0).getMBB();
            return false;
        }
    }
    default: 
        // if some another branch, it's unknown brach
        // if not brannch, it's fallthourgh
        if (lastIns.getDesc().isBranch()) {
            tbb = lastIns.getOperand(2).getMBB();
            return plugin_->analyzeCCBranch(lastIns, cond);
        } else {
            return false;
        }
    }
    // should never be here
    return true;
}

References llvm::TCETargetMachinePlugin::analyzeCCBranch(), assert, and plugin_.

Referenced by loadRegFromStackSlot().

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◆ analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > TCEInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const

override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 565 of file TCEInstrInfo.cc.

                                                                      {
    return std::make_unique<TCEPipelinerLoopInfo>();
}

Referenced by loadRegFromStackSlot().

◆ BlockHasNoFallThrough()

bool TCEInstrInfo::BlockHasNoFallThrough ( const MachineBasicBlock & MBB ) const

virtual

Returns true if program control can't fall through the last instruction in the basic block, false otherwise.

Definition at line 196 of file TCEInstrInfo.cc.

                                                                      {
    /* Mips inspired */
    if (MBB.empty()) return false;
    switch (MBB.back().getOpcode()) {
    case TCE::RETL:    // Return.
    case TCE::TCEBR:  // Uncond branch.
    case TCE::TCEBRIND:  // Uncond indirect branch.
        return true;
    default: return false;
    }
}

◆ ClobbersPredicate()

bool TCEInstrInfo::ClobbersPredicate	(	MachineInstr &	MI,
		std::vector< MachineOperand > &	Pred,
		bool	SkipDead
	)		const

overridevirtual

Definition at line 691 of file TCEInstrInfo.cc.

                         {
    for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
        MachineOperand MO = MI.getOperand(oper);
        if (MO.isReg() && MO.isDef()) {
            const TargetRegisterClass* RC =
                ri_.getMinimalPhysRegClass(MO.getReg());
            if (RC == &TCE::GuardRegsRegClass || RC == &TCE::R1RegsRegClass) {
                Pred.push_back(MO);
                return true;
            }
        }
    }
    return false;
}

References ri_.

Referenced by loadRegFromStackSlot().

◆ copyPhysReg()

void TCEInstrInfo::copyPhysReg	(	MachineBasicBlock &	mbb,
		MachineBasicBlock::iterator	mbbi,
		const DebugLoc &	DL,
		MCRegister	destReg,
		MCRegister	srcReg,
		bool	killSrc
	)		const

overridevirtual

Creates instruction for copying value from a register to another.

Parameters

mbb	Basic block where the copy is done.
mbbi	Iterator to the place where the copy instruction is added.
srcReg	Register where the value is copied from.
destReg	Register where the value is copied to.
rc	Class of the register to copy.

Definition at line 264 of file TCEInstrInfo.cc.

{
    DebugLoc dl;
    if (mbbi != mbb.end()) dl = mbbi->getDebugLoc();
/*
    BuildMI(mbb, mbbi, dl, 
            get(plugin_->getRegCopy(destReg, srcReg)), destReg).
        .addReg(SrcReg, getKillRegState(isKillSrc));
*/
    if (copyPhysVectorReg(mbb, mbbi, dl, destReg, srcReg, killSrc)) {
        return;
    }
 
    if (TCE::R1RegsRegClass.contains(destReg, srcReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVI1rr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::R32IRegsRegClass.contains(destReg, srcReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVI32rr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::R64RegsRegClass.contains(destReg, srcReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOV64ss), destReg)
        .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::FPRegsRegClass.contains(destReg, srcReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVff), destReg)
        .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::HFPRegsRegClass.contains(destReg, srcReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVhh), destReg)
        .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::R1RegsRegClass.contains(destReg) &&
               TCE::R32IRegsRegClass.contains(srcReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVI32I1rr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::R1RegsRegClass.contains(srcReg) &&
               TCE::R32IRegsRegClass.contains(destReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVI1I32rr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::GuardRegsRegClass.contains(destReg, srcReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVGrr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::GuardRegsRegClass.contains(srcReg) &&
               TCE::R32IRegsRegClass.contains(destReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVGI32rr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::R32IRegsRegClass.contains(srcReg) &&
               TCE::GuardRegsRegClass.contains(destReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVI32Grr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::GuardRegsRegClass.contains(srcReg) &&
               TCE::R1RegsRegClass.contains(destReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVGI1rr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else if (TCE::R1RegsRegClass.contains(srcReg) &&
               TCE::GuardRegsRegClass.contains(destReg)) {
        BuildMI(mbb, mbbi, dl, get(TCE::MOVI1Grr), destReg)
            .addReg(srcReg, getKillRegState(killSrc));
    } else {
        assert(
            false && "TCERegisterInfo::copyPhysReg(): Can't copy register");
 
    }
}

References assert, and copyPhysVectorReg().

Referenced by loadRegFromStackSlot().

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◆ copyPhysVectorReg()

bool llvm::TCEInstrInfo::copyPhysVectorReg	(	MachineBasicBlock &	mbb,
		MachineBasicBlock::iterator	mbbi,
		const DebugLoc &	DL,
		MCRegister	destReg,
		MCRegister	srcReg,
		bool	killSrc
	)		const

private

Referenced by copyPhysReg().

◆ CreateTargetScheduleState()

DFAPacketizer * TCEInstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const

overridevirtual

Definition at line 737 of file TCEInstrInfo.cc.

                                          {
    const InstrItineraryData *II = STI.getInstrItineraryData();
    DFAPacketizer *dfa =
        static_cast<const TCESubtarget &>(STI).createDFAPacketizer(II);
    assert(dfa != nullptr);
    return dfa;
}

References assert.

◆ getInstrItineraryData()

const InstrItineraryData * llvm::TCEInstrInfo::getInstrItineraryData ( ) const

inline

Definition at line 63 of file TCEInstrInfo.hh.

                                      {
            return &InstrItins;
        }

References InstrItins.

◆ getMatchingCondBranchOpcode()

int TCEInstrInfo::getMatchingCondBranchOpcode	(	int	Opc,
		bool	inverted
	)		const

private

Definition at line 680 of file TCEInstrInfo.cc.

                                                                     {
    
    if (!inv) {
        return plugin_->getTruePredicateOpcode(opc);
    } else {
        return plugin_->getFalsePredicateOpcode(opc);
    }
}

References llvm::TCETargetMachinePlugin::getFalsePredicateOpcode(), llvm::TCETargetMachinePlugin::getTruePredicateOpcode(), and plugin_.

Referenced by isPredicable(), and PredicateInstruction().

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◆ getPointerAdjustment()

std::tuple< int, int > TCEInstrInfo::getPointerAdjustment ( int offset ) const

Return opcode for pointer adjustment and new offset.

Returns opcode available or suitable for pointer adjustment with constant offset value.

Parameters

offset The offset for the pointer.

Returns: (opcode, new offset) tuple.

Definition at line 732 of file TCEInstrInfo.cc.

                                                   {
    return plugin_->getPointerAdjustment(offset);
}

References llvm::TCETargetMachinePlugin::getPointerAdjustment(), and plugin_.

Referenced by llvm::TCEFrameLowering::eliminateCallFramePseudoInstr(), llvm::TCERegisterInfo::eliminateFrameIndex(), and llvm::TCEFrameLowering::emitPrologue().

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◆ getRegisterInfo()

virtual const TargetRegisterInfo & llvm::TCEInstrInfo::getRegisterInfo ( ) const

inlinevirtual

Definition at line 67 of file TCEInstrInfo.hh.

                                                                  { 
            return ri_; 
        }

References ri_.

Referenced by llvm::GeneratedTCEPlugin::getRegisterInfo().

◆ insertBranch()

unsigned TCEInstrInfo::insertBranch	(	MachineBasicBlock &	mbb,
		MachineBasicBlock *	tbb,
		MachineBasicBlock *	fbb,
		ArrayRef< MachineOperand >	cond,
		const DebugLoc &	dl,
		int *	BytesAdded = `nullptr`
	)		const

overridevirtual

Inserts a branch instruction or brach instructions into llvm MBB.

If the MBB already has an unconditional branch at end, does nothing.

Parameters

mbb	where to insert the branch instructions.
tbb	jump target basic block
fbb	false condition jump target, if insertin 2 branches

Returns: number of branch instructions inserted

Definition at line 97 of file TCEInstrInfo.cc.

                             {
    assert(cond.size() == 0 || cond.size() == 2 || cond.size() == 3);
 
    if (mbb.size() != 0) {
        // already has a uncond branch, no need for another.
        // asserts to make sure it's to same BB in order to not create
        // broken code.
        if (mbb.back().getOpcode() == TCE::TCEBR ||
            mbb.back().getOpcode() == TCE::TCEBRIND) { 
            assert(cond.size() == 0);
            return 0;
        }
        if (cond.size() != 0) {
            assert (mbb.back().getOpcode() != TCE::TCEBRCOND && "c branch!");
            assert (mbb.back().getOpcode() != TCE::TCEBRICOND && "ic branch!");
            assert (mbb.back().getOpcode() != TCE::TCEBR && "has branch!(1)");
        } else {
            assert (mbb.back().getOpcode() != TCE::TCEBR && "has branch(2)!");
        }
 
    }
 
    if (fbb == 0) {
        if (cond.empty()) {
            // Can only insert uncond branches so far.
            BuildMI(&mbb, dl, get(TCE::TCEBR)).addMBB(tbb);
            return 1;
        } else {
            if (cond.size() == 2 && cond[1].getImm() == false) {
                // false jump
                BuildMI(&mbb, dl, get(TCE::TCEBRICOND)).
                    addReg(cond[0].getReg()).addMBB(tbb);
                return 1;
            } else if (cond.size() == 2 && cond[1].getImm() == true) {
                BuildMI(&mbb, dl, get(TCE::TCEBRCOND)).addReg(cond[0].getReg())
                    .addMBB(tbb);
                return 1;
            } else {
                insertCCBranch(mbb, *tbb, cond, dl);
                return 1;
            }
        }
    }
 
    assert(
        !cond.empty() &&
        "Two jumps need a condition");  // not allowed to have conditional
                                        // jump because we have an fbb
 
    if (cond.size() == 2 && cond[1].getImm() == false) {
        BuildMI(&mbb, dl, get(TCE::TCEBRICOND)).
            addReg(cond[0].getReg()).addMBB(tbb);
    } else if (cond.size() == 1 ||
               (cond.size() == 2 && cond[1].getImm() == true)) {
        BuildMI(&mbb, dl, get(TCE::TCEBRCOND)).
            addReg(cond[0].getReg()).addMBB(tbb);
    } else {
        insertCCBranch(mbb, *tbb, cond, dl);
    }
    BuildMI(&mbb, dl, get(TCE::TCEBR)).addMBB(fbb);
 
    return 2;
}

References assert, and insertCCBranch().

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◆ insertCCBranch()

virtual void llvm::TCEInstrInfo::insertCCBranch	(	MachineBasicBlock &	mbb,
		MachineBasicBlock &	tbb,
		ArrayRef< MachineOperand >	cond,
		const DebugLoc &	dl
	)		const

virtual

Referenced by insertBranch().

◆ isPredicable()

bool TCEInstrInfo::isPredicable ( const MachineInstr & MI ) const

overridevirtual

Definition at line 587 of file TCEInstrInfo.cc.

                                                           {
    const MachineInstr* mi = &mi_ref;
    if (mi->getOpcode() == TCE::COPY) {
        return false;
    }
 
    // TODO: why is RETL not predicable?
    if (mi->getOpcode() == TCE::RETL) {
        return false;
    }
 
    if (isPredicated(*mi)) {
        return false;
    }
 
    if (getMatchingCondBranchOpcode(mi->getOpcode(),false) == -1) {
        return false;
    }
 
    for (int oper = mi->getNumOperands() - 1; oper >= 0; --oper) {
        MachineOperand mo = mi->getOperand(oper);
 
        if ((mo.isReg() && !mo.isUse() && !mo.isImplicit())) {
            continue;
        }
 
        // TODO: support operand changing for fp imms etc.!
        if (!mo.isReg() && !mo.isImm()) {
            return false;
        }
    }
    return true;
}

References getMatchingCondBranchOpcode(), and isPredicated().

Referenced by loadRegFromStackSlot(), and PredicateInstruction().

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◆ isPredicated()

bool TCEInstrInfo::isPredicated ( const MachineInstr & MI ) const

overridevirtual

Definition at line 570 of file TCEInstrInfo.cc.

                                                           {
    const MachineInstr* mi = &mi_ref;
    // TODO: should be conditional move here..
    if (mi->getOpcode() == TCE::RETL) {
        return false;
    }
 
    // KILL is not a predicated instruction.
    if (mi->getOpcode() == TCE::KILL) {
        return false;
    }
 
    TCEString opName = plugin_->operationName(mi->getOpcode());
    return opName[0] == '?' || opName[0] == '!';
}

References llvm::TCETargetMachinePlugin::operationName(), and plugin_.

Referenced by isPredicable(), and loadRegFromStackSlot().

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◆ isProfitableToIfCvt() [1/2]

bool TCEInstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	MBB,
		unsigned	NumCycles,
		unsigned	ExtraPredCycles,
		BranchProbability	Probability
	)		const

overridevirtual

Definition at line 709 of file TCEInstrInfo.cc.

                                                         {
    return true;
}

◆ isProfitableToIfCvt() [2/2]

bool TCEInstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	TMBB,
		unsigned	NumTCycles,
		unsigned	ExtraTCycles,
		MachineBasicBlock &	FMBB,
		unsigned	NumFCycles,
		unsigned	ExtraFCycles,
		BranchProbability	Probability
	)		const

overridevirtual

Definition at line 719 of file TCEInstrInfo.cc.

                                                         {
    return true;
}

◆ loadRegFromStackSlot() [1/2]

virtual void llvm::TCEInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	mbb,
		MachineBasicBlock::iterator	mbbi,
		Register	destReg,
		int	frameIndex,
		const TargetRegisterClass *	rc,
		const TargetRegisterInfo *	,
		Register	vReg
	)		const

inlineoverridevirtual

Definition at line 122 of file TCEInstrInfo.hh.

                                                                                     {
            loadRegFromStackSlot(mbb, mbbi, destReg, frameIndex, rc);
            #else
            const TargetRegisterClass* rc, const TargetRegisterInfo*,
            Register vReg) const override {
            loadRegFromStackSlot(mbb, mbbi, destReg, frameIndex, rc, 0);
            #endif
        }

References analyzeBranch(), analyzeLoopForPipelining(), ClobbersPredicate(), copyPhysReg(), isPredicable(), isPredicated(), loadRegFromStackSlot(), PredicateInstruction(), and reverseBranchCondition().

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◆ loadRegFromStackSlot() [2/2]

void TCEInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	mbb,
		MachineBasicBlock::iterator	mbbi,
		unsigned	destReg,
		int	frameIndex,
		const TargetRegisterClass *	rc,
		Register	vReg
	)		const

virtual

Definition at line 232 of file TCEInstrInfo.cc.

                                                          {
                     #else
                     const TargetRegisterClass *RC, Register vReg) const {
                     #endif
  DebugLoc DL;
 
  if (I != MBB.end()) DL = I->getDebugLoc();
  BuildMI(MBB, I, DL, get(plugin_->getLoad(RC)), DestReg).addFrameIndex(FI)
      .addImm(0);
 
  LLVMContext& context = MBB.getParent()->getFunction().getContext();
  llvm::Metadata* md = llvm::MDString::get(context, "AA_CATEGORY_STACK_SLOT");
  MDNode* mdNode =
      MDNode::get(context, llvm::ArrayRef<llvm::Metadata*>(&md, 1));
  MachineOperand metaDataOperand = MachineOperand::CreateMetadata(mdNode);
  I--; // buildmi moves the iterator to next ins, point to the created one.
  I->addOperand(metaDataOperand);
}

References llvm::TCETargetMachinePlugin::getLoad(), and plugin_.

Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().

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◆ PredicateInstruction()

bool TCEInstrInfo::PredicateInstruction	(	MachineInstr &	mi,
		ArrayRef< MachineOperand >	cond
	)		const

overridevirtual

Definition at line 623 of file TCEInstrInfo.cc.

        {
 
    MachineInstr *mi = &mi_ref;
 
    int opc = mi->getOpcode();
 
    assert (isPredicable(*mi) && "Expected predicable instruction");
 
    bool invertJump = (cond.size() >1 && cond[1].isImm() &&
                       (cond[1].getImm() == 0));
    
    mi->setDesc(get(getMatchingCondBranchOpcode(opc, invertJump)));
    //
    // This assumes that the predicate is always the first operand
    // in the set of inputs.
    //
    mi->addOperand(mi->getOperand(mi->getNumOperands()-1));
    int oper;
    // why -3 in hexagon?
    for (oper = mi->getNumOperands() - 2; oper >= 0; --oper) {
        MachineOperand mo = mi->getOperand(oper);
    // todo: why this break in hexagon?
        if ((mo.isReg() && !mo.isUse() && !mo.isImplicit())) {
            break;
        }
 
        if (mo.isReg()) {
            mi->getOperand(oper+1).ChangeToRegister(mo.getReg(), mo.isDef(),
                            mo.isImplicit(), mo.isKill(),
                            mo.isDead(), mo.isUndef(),
                            mo.isDebug());
        } else if (mo.isImm()) {
            mi->getOperand(oper+1).ChangeToImmediate(mo.getImm());
        } else if (mo.isFPImm()) {
            mi->getOperand(oper+1).ChangeToFPImmediate(mo.getFPImm());
        } else if (mo.isGlobal()) {
            // TODO: what to do here?
            llvm_unreachable("Unexpected operand type");
            mi->getOperand(oper+1).ChangeToImmediate(mo.getImm());
        } else {
            llvm_unreachable("Unexpected operand type");
        }
    }
 
    MachineOperand PredMO = cond[0];
    mi->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
                                            PredMO.isImplicit(), PredMO.isKill(),
                                            PredMO.isDead(), PredMO.isUndef(),
                                            PredMO.isDebug());
    
    return true;
}

References assert, getMatchingCondBranchOpcode(), and isPredicable().

Referenced by loadRegFromStackSlot().

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◆ removeBranch()

unsigned TCEInstrInfo::removeBranch	(	MachineBasicBlock &	mbb,
		int *	BytesRemoved = `nullptr`
	)		const

override

Removes branch or branches form end of llvm MachineBasicBlock

Parameters

mbb	where to remove the branches from

Returns: number of braches removed

Definition at line 174 of file TCEInstrInfo.cc.

                                                     {
    int j = 0;
    MachineBasicBlock::iterator i = mbb.end();
    while (i != mbb.begin()) {
        i--;
        int opc = i->getOpcode();
        if (i->getDesc().isBranch()) {
            i->eraseFromParent();
            i = mbb.end();  // not optimal, but we will not miss any
                            // instruction
            j++;
        }
    }
    return j;
}

◆ reverseBranchCondition()

bool TCEInstrInfo::reverseBranchCondition ( llvm::SmallVectorImpl< llvm::MachineOperand > & cond ) const

overridevirtual

Definition at line 339 of file TCEInstrInfo.cc.

                                                         {
    assert(cond.size() != 0);
 
    // from true to false
    if (cond.size() == 1) {
        cond.push_back(MachineOperand::CreateImm(false));
        return false;
    } else if (cond.size() == 2) {
        // from false to true
        if (cond[1].getImm() == false) {
            cond[1].setImm(true);
        } else {
            // from true to false
            assert(cond[1].getImm() == true);
            cond[1].setImm(false);
        }
        return false;
    } else if (cond.size() == 3) {
        switch (cond[2].getImm()) {
        case 2:
            // eq -> ne
            cond[2].setImm(3);
            return false;
        case 3:
            // ne -> eq
            cond[2].setImm(2);
            return false;
        case 4:
            // gt -> le
            cond[2].setImm(5);
            return false;
        case 5:
            // le -> gt
            cond[2].setImm(4);
            return false;
        case 6:
            // ltu -> geu
            cond[2].setImm(7);
            return false;
        case 7:
            // geu -> ltu
            cond[2].setImm(6);
            return false;
        case 14:
            // lt -> ge
            cond[2].setImm(16);
            return false;
        case 15:
            // ltu -> geu
            cond[2].setImm(17);
            return false;
        case 16:
            // ge -> lt
            cond[2].setImm(14);
            return false;
        case 17:
            // geu -> ltu
            cond[2].setImm(15);
            return false;
        // case 100+: register-immediate versions of branch ops
        case 102:
            // eg -> ne
            cond[2].setImm(103);
            return false;
        case 103:
            // ne -> eq
            cond[2].setImm(102);
            return false;
        case 104:
            // gt -> le
            cond[2].setImm(105);
            return false;
        case 105:
            // le -> gt
            cond[2].setImm(104);
            return false;
        case 106:
            // ltu -> geu
            cond[2].setImm(107);
            return false;
        case 107:
            // geu -> ltu
            cond[2].setImm(106);
            return false;
        case 114:
            // lt -> ge
            cond[2].setImm(116);
            return false;
        case 115:
            // ltu -> geu
            cond[2].setImm(117);
            return false;
        case 116:
            // ge -> lt
            cond[2].setImm(114);
            return false;
        case 117:
            // geu -> ltu
            cond[2].setImm(115);
            return false;
        default:
            return true;
        }
    }
    return true;
}

References assert.

Referenced by loadRegFromStackSlot().

◆ storeRegToStackSlot() [1/2]

virtual void llvm::TCEInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	mbb,
		MachineBasicBlock::iterator	mbbi,
		Register	srcReg,
		bool	isKill,
		int	frameIndex,
		const TargetRegisterClass *	rc,
		const TargetRegisterInfo *	,
		Register	vReg
	)		const

inlineoverridevirtual

Definition at line 95 of file TCEInstrInfo.hh.

                                                                                     {
            storeRegToStackSlot(mbb, mbbi, srcReg, isKill, frameIndex, rc);
            #else
            const TargetRegisterClass* rc, const TargetRegisterInfo*,
            Register vReg) const override {
            storeRegToStackSlot(mbb, mbbi, srcReg, isKill, frameIndex, rc, 0);
            #endif
        }

References loadRegFromStackSlot(), and storeRegToStackSlot().

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◆ storeRegToStackSlot() [2/2]

void TCEInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	mbb,
		MachineBasicBlock::iterator	mbbi,
		unsigned	srcReg,
		bool	isKill,
		int	frameIndex,
		const TargetRegisterClass *	rc,
		Register	vReg
	)		const

virtual

Definition at line 208 of file TCEInstrInfo.cc.

                                                         {
                    #else
                    const TargetRegisterClass *RC, Register vReg) const {
                    #endif
  DebugLoc DL;
 
  if (I != MBB.end()) DL = I->getDebugLoc();
 
  BuildMI(MBB, I, DL, get(plugin_->getStore(RC))).addFrameIndex(FI).addImm(0)
      .addReg(SrcReg, getKillRegState(isKill));
 
  LLVMContext& context = MBB.getParent()->getFunction().getContext();
  llvm::Metadata* md = llvm::MDString::get(context, "AA_CATEGORY_STACK_SLOT");
  MDNode* mdNode =
      MDNode::get(context, llvm::ArrayRef<llvm::Metadata*>(&md, 1));
  MachineOperand metaDataOperand = MachineOperand::CreateMetadata(mdNode);
  I--; // buildmi moves the iterator to next ins, point to the created one.
  I->addOperand(metaDataOperand);
}

References llvm::TCETargetMachinePlugin::getStore(), and plugin_.

Referenced by storeRegToStackSlot().

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◆ SubsumesPredicate()

virtual bool llvm::TCEInstrInfo::SubsumesPredicate	(	ArrayRef< MachineOperand >	Pred1,
		ArrayRef< MachineOperand >	Pred2
	)		const

inlineoverridevirtual

Definition at line 171 of file TCEInstrInfo.hh.

                                                       {
        return false;
    }

Member Data Documentation

◆ InstrItins

InstrItineraryData llvm::TCEInstrInfo::InstrItins

private

Definition at line 208 of file TCEInstrInfo.hh.

Referenced by getInstrItineraryData().

◆ plugin_

const TCETargetMachinePlugin* llvm::TCEInstrInfo::plugin_

private

Definition at line 213 of file TCEInstrInfo.hh.

Referenced by analyzeBranch(), getMatchingCondBranchOpcode(), getPointerAdjustment(), isPredicated(), loadRegFromStackSlot(), and storeRegToStackSlot().

◆ ri_

const TCERegisterInfo llvm::TCEInstrInfo::ri_

private

Definition at line 212 of file TCEInstrInfo.hh.

Referenced by ClobbersPredicate(), and getRegisterInfo().

The documentation for this class was generated from the following files:

Public Member Functions

Private Member Functions

Private Attributes

Detailed Description

Constructor & Destructor Documentation

◆ TCEInstrInfo()

◆ ~TCEInstrInfo()

Member Function Documentation

◆ analyzeBranch()

◆ analyzeLoopForPipelining()

◆ BlockHasNoFallThrough()

◆ ClobbersPredicate()

◆ copyPhysReg()

◆ copyPhysVectorReg()

◆ CreateTargetScheduleState()

◆ getInstrItineraryData()

◆ getMatchingCondBranchOpcode()

◆ getPointerAdjustment()

◆ getRegisterInfo()

◆ insertBranch()

◆ insertCCBranch()

◆ isPredicable()

◆ isPredicated()

◆ isProfitableToIfCvt() [1/2]

◆ isProfitableToIfCvt() [2/2]

◆ loadRegFromStackSlot() [1/2]

◆ loadRegFromStackSlot() [2/2]

◆ PredicateInstruction()

◆ removeBranch()

◆ reverseBranchCondition()

◆ storeRegToStackSlot() [1/2]

◆ storeRegToStackSlot() [2/2]

◆ SubsumesPredicate()

Member Data Documentation

◆ InstrItins

◆ plugin_

◆ ri_