OpenASIP 2.2
Loading...
Searching...
No Matches
TCETargetMachinePlugin.cc
Go to the documentation of this file.
1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file TCETargetMachinePlugin.cc
26 *
27 * Implementation of TCETargetMachinePlugin class.
28 *
29 * @author Veli-Pekka Jääskeläinen 2007 (vjaaskel-no.spam-cs.tut.fi)
30 * @author Mikael Lepistö 2009 (mikael.lepisto-no.spam-tut.fi)
31 * @author Pekka Jääskeläinen 2012
32 * @note rating: red
33 */
34
35//#include <llvm/Config/config.h>
36#include <string>
37#include <iostream>
38#include <sstream>
40#include "TCEPlugin.hh"
41#include "TCETargetMachine.hh"
42#include "TCEFrameInfo.hh"
43#include "TCEISelLowering.hh"
44#include "TCESubtarget.hh"
45#include "MapTools.hh"
46#include "CIStringSet.hh"
50
51using namespace llvm;
52
53using std::string;
54
55namespace llvm {
57public:
59 virtual ~GeneratedTCEPlugin();
60 virtual const TargetInstrInfo* getInstrInfo() const override;
61 virtual const TargetRegisterInfo* getRegisterInfo() const override;
62 virtual const TargetFrameLowering* getFrameLowering() const override;
63 virtual TargetLowering* getTargetLowering() const override;
64 virtual TargetTransformInfo getTargetTransformInfo(
65 const Function& F) const override;
66 virtual const TargetSubtargetInfo* getSubtarget() const override;
67
68 virtual FunctionPass* createISelPass(TCETargetMachine* tm) override;
69
70 virtual unsigned spDRegNum() override {
71 return TCE::SP;
72 }
73
74 virtual unsigned fpDRegNum() override {
75 return TCE::FP;
76 }
77
78 virtual unsigned rvDRegNum() override {
79 return TCE::IRES0;
80 }
81
82 virtual unsigned rvHighDRegNum() override {
83 return TCE::KLUDGE_REGISTER;
84 }
85
86 virtual std::vector<unsigned> getParamDRegNums() const override;
87
88 virtual std::vector<unsigned> getVectorRVDRegNums() const override;
89
90 virtual MVT::SimpleValueType getDefaultType() const override {
91#ifdef TARGET64BIT
92 return MVT::i64;
93#else
94 return MVT::i32;
95#endif
96 }
97 virtual std::string rfName(unsigned dwarfRegNum) override;
98 virtual unsigned registerIndex(unsigned dwarfRegNum) override;
99
100 unsigned llvmRegisterId(const TCEString& ttaRegister) override {
101 if (ttallvmRegMap_.count(ttaRegister)) {
102 return ttallvmRegMap_[ttaRegister];
103 }
104 return TCE::NoRegister;
105 }
106
107 unsigned int extractElementLane(const llvm::MachineInstr&) const override;
108
109 virtual std::string operationName(unsigned opc) const override;
110 virtual bool validStackAccessOperation(
111 const std::string& opName) const override;
112
113 virtual bool hasOperation(TCEString operationName) const override {
115 }
116
117 virtual unsigned opcode(TCEString operationName) const override {
119 }
120
121 virtual int getTruePredicateOpcode(unsigned opc) const override;
122 virtual int getFalsePredicateOpcode(unsigned opc) const override;
123
124 unsigned int raPortDRegNum() override;
125 std::string dataASName() override;
126
127 virtual bool hasSDIV() const override;
128 virtual bool hasUDIV() const override;
129 virtual bool hasSREM() const override;
130 virtual bool hasUREM() const override;
131 virtual bool hasMUL() const override;
132 virtual bool hasROTL() const override;
133 virtual bool hasROTR() const override;
134 virtual bool hasSXHW() const override;
135 virtual bool hasSXQW() const override;
136 virtual bool hasSQRTF() const override;
137 virtual bool hasSHR() const override;
138 virtual bool hasSHL() const override;
139 virtual bool hasSHRU() const override;
140 virtual bool has8bitLoads() const override;
141 virtual bool has16bitLoads() const override;
142
143 virtual int maxVectorSize() const override;
144
145 virtual bool analyzeCCBranch(
146 llvm::MachineInstr& i,
147 llvm::SmallVectorImpl<llvm::MachineOperand>& cond) const override;
148
149 virtual void registerTargetMachine(TCETargetMachine &tm) override;
150
151 virtual int getLoad(const TargetRegisterClass *rc) const override;
152 virtual int getStore(const TargetRegisterClass *rc) const override;
153
154 virtual int getMinOpcode(llvm::SDNode* n) const override;
155 virtual int getMaxOpcode(llvm::SDNode* n) const override;
156 virtual int getMinuOpcode(llvm::SDNode* n) const override;
157 virtual int getMaxuOpcode(llvm::SDNode* n) const override;
158
159 virtual const llvm::TargetRegisterClass* extrasRegClass(
160 const llvm::TargetRegisterClass* current) const override;
161 virtual const llvm::TargetRegisterClass* nodeRegClass(
162 unsigned nodeId,
163 const llvm::TargetRegisterClass* current) const override;
164
165 virtual int getLoadOpcode(const EVT& vt) const override;
166 // -1 or vector add opcode. Implementation generated to Backend.inc
167 virtual int getAddOpcode(const EVT& vt) const override;
168 // -1 or vector shl opcode. Implementation generated to Backend.inc
169 virtual int getShlOpcode(const EVT& vt) const override;
170 // -1 or vector or opcode. Implementation generated to Backend.inc
171 virtual int getIorOpcode(const EVT& vt) const override;
172
173 // If machine is little-endian.
174 virtual bool isLittleEndian() const override;
175 virtual bool is64bit() const override;
176
177 // Returns true if the constant value can be materialized. Implementation
178 // is generated to Backend.inc
179 virtual bool canMaterializeConstant(const ConstantInt& ci) const override;
180
181 virtual std::tuple<int, int> getPointerAdjustment(
182 int offset) const override;
183 virtual void manualInitialize();
184
185private:
187
188 std::map<unsigned, TCEString> opNames_;
189 std::map<unsigned, unsigned> truePredOps_;
190 std::map<unsigned, unsigned> falsePredOps_;
191 std::map<unsigned, TCEString> regNames_;
192 std::map<unsigned, unsigned> regIndices_;
193 /// Map for TTA register to LLVM register id conversion.
194 std::map<TCEString, unsigned> ttallvmRegMap_;
195 /// Set of valid LLVM opcodes for stack accesses.
197
198 std::string dataASName_;
199};
200}
201
202#include "Backend.inc"
203
204
205// This global class initialization hack is needed to pass the adf data to the
206// middle-end, which provides details for llvm autovectorization.
208public:
210
212 plugin->manualInitialize();
213
214 // Register LLVM Target and TCE Stub TargetMachine
217 }
219
220/**
221 * The Constructor.
222 */
227
228
229/**
230 * The Destructor.
231 */
233 delete instrInfo_;
234 if (lowering_ != NULL) {
235 delete lowering_;
236 lowering_ = NULL;
237 }
238}
239
240void
244
245void
247 TCETargetMachine &tm) {
248 tm_ = &tm;
249 instrInfo_ = new TCEInstrInfo(this);
250 // Initialize register & opcode maps.
251 initialize();
252
253 TCERegisterInfo* ri =
254 const_cast<TCERegisterInfo*>(
255 static_cast<const TCERegisterInfo*>(getRegisterInfo()));
257
258 if (isLittleEndian()) {
259#ifndef TARGET64BIT
260 subTarget_ = new TCELESubtarget(this);
261#else
262 subTarget_ = new TCELE64Subtarget(this);
263#endif
264 } else {
265 subTarget_ = new TCESubtarget(this);
266 }
267
268 if (lowering_ == NULL) {
270 }
271}
272
273/**
274 * Returns TargetInstrInfo object for TCE target.
275 */
276const TargetInstrInfo*
280
281/**
282 * Returns TargetRegisterInfo object for TCE target.
283 */
284const TargetRegisterInfo*
286 return &(static_cast<TCEInstrInfo*>(instrInfo_))->getRegisterInfo();
287}
288
289/**
290 * Returns TargetFrameInfo object for TCE target.
291 */
292const TargetFrameLowering*
296
297TargetTransformInfo
299 return TargetTransformInfo(TCETTIImpl(tm_, F));
300}
301
302/**
303 * Returns TargetLowering object for TCE target.
304 */
305TargetLowering*
307 assert(lowering_ != NULL && "TCETargetMachine has not registered to plugin.");
308 return lowering_;
309}
310
311const TargetSubtargetInfo*
315
316/**
317 * Creates instruction selector for TCE target machine.
318 */
319FunctionPass*
323
324/**
325 * Returns true in case the given opc is for an extract element
326 * operation.
327 */
328unsigned int
329GeneratedTCEPlugin::extractElementLane(const llvm::MachineInstr& mi) const {
330 // TODO: use subregisters (extract_subreg) instead.
331 if (mi.getDesc().getOpcode() == TCE::COPY) {
332 assert(mi.getNumOperands() >= 2);
333 const MachineOperand& src = mi.getOperand(1);
334 int subreg = src.getSubReg();
335 if (subreg > 0 && subreg < 9) {
336 return subreg -1;
337 }
338 }
339 return UINT_MAX;
340}
341
343 std::map<unsigned int, unsigned int>::const_iterator i = truePredOps_.find(opc);
344 if (i == truePredOps_.end()) {
345 return -1;
346 } else {
347 return i->second;
348 }
349}
350
352 std::map<unsigned int, unsigned int>::const_iterator i = falsePredOps_.find(opc);
353 if (i == falsePredOps_.end()) {
354 return -1;
355 } else {
356 return i->second;
357 }
358}
359
360/**
361 * Maps llvm target opcodes to target operation names.
362 *
363 * Returns an empty string in case the operation code could not be
364 * mapped to an OSAL operation name. This is the case with pseudo
365 * ops, for example.
366 */
367std::string
369
370 const std::string MOVE = "MOVE";
371 const std::string PSEUDO = "PSEUDO";
372 const std::string NOP = "NOP";
373 const std::string INLINEASM = "INLINEASM";
374 const std::string DEBUG_LABEL = "DEBUG_LABEL";
375 const std::string DEBUG_VALUE = "DEBUG_VALUE";
376 const std::string DEBUG_INSTR_REF = "DEBUG_INSTR_REF";
377 const std::string DEBUG_VALUE_LIST = "DEBUG_VALUE_LIST";
378 const std::string DEBUG_PHI = "DEBUG_PHI";
379
380 if (opc == TCE::IMPLICIT_DEF) return PSEUDO;
381 else if (opc == TCE::ADJCALLSTACKDOWN) return PSEUDO;
382 else if (opc == TCE::ADJCALLSTACKUP) return PSEUDO;
383 else if (opc == TCE::NOP) return NOP;
384 if (opc == TCE::DBG_VALUE) return DEBUG_VALUE;
385 if (opc == TCE::DBG_INSTR_REF) return DEBUG_INSTR_REF;
386 if (opc == TCE::DBG_LABEL) return DEBUG_LABEL;
387 if (opc == TCE::DBG_VALUE_LIST) return DEBUG_VALUE_LIST;
388 if (opc == TCE::DBG_PHI) return DEBUG_PHI;
389 // Moves
390 if (opc == TCE::COPY) return MOVE;
391 if (opc == TCE::MOVI1rr) return MOVE;
392 if (opc == TCE::PRED_TRUE_MOVI1rr) return "?MOVE";
393 if (opc == TCE::PRED_FALSE_MOVI1rr) return "!MOVE";
394 if (opc == TCE::MOVI1ri) return MOVE;
395 if (opc == TCE::PRED_TRUE_MOVI1ri) return "?MOVE";
396 if (opc == TCE::PRED_FALSE_MOVI1ri) return "!MOVE";
397 if (opc == TCE::MOVGri) return MOVE;
398 if (opc == TCE::MOVI32rr) return MOVE;
399 if (opc == TCE::PRED_TRUE_MOVI32rr) return "?MOVE";
400 if (opc == TCE::PRED_FALSE_MOVI32rr) return "!MOVE";
401 if (opc == TCE::MOVI32ri) return MOVE;
402 if (opc == TCE::PRED_TRUE_MOVI32ri) return "?MOVE";
403 if (opc == TCE::PRED_FALSE_MOVI32ri) return "!MOVE";
404 if (opc == TCE::MOVI64sa) return MOVE;
405 if (opc == TCE::PRED_TRUE_MOVI64sa) return "?MOVE";
406 if (opc == TCE::PRED_FALSE_MOVI64sa) return "!MOVE";
407 if (opc == TCE::MOV64ss) return MOVE;
408 if (opc == TCE::PRED_TRUE_MOV64ss) return "?MOVE";
409 if (opc == TCE::PRED_FALSE_MOV64ss) return "!MOVE";
410 if (opc == TCE::MOVI64I1ss) return MOVE;
411
412 // TODO: why no predicated version of this?
413 if (opc == TCE::MOVff) return MOVE;
414 if (opc == TCE::MOVfi) return MOVE;
415 if (opc == TCE::MOVfk) return MOVE;
416 if (opc == TCE::MOVI32I1rr) return MOVE;
417 if (opc == TCE::MOVFI32rf) return MOVE;
418 if (opc == TCE::MOVIF32fr) return MOVE;
419 if (opc == TCE::MOVGrr) return MOVE;
420 if (opc == TCE::MOVGI32rr) return MOVE;
421 if (opc == TCE::MOVI32Grr) return MOVE;
422 if (opc == TCE::MOVGI1rr) return MOVE;
423 if (opc == TCE::MOVI1Grr) return MOVE;
424 if (opc == TCE::MOVhh) return MOVE;
425 if (opc == TCE::MOVhk) return MOVE;
426 if (opc == TCE::MOVrh) return MOVE;
427 if (opc == TCE::MOVhr) return MOVE;
428 if (opc == TCE::MOVhi) return MOVE;
429 if (opc == TCE::MOVsd) return MOVE;
430 if (opc == TCE::MOVds) return MOVE;
431
432 // TODO: added as a spot fix for simd_operations_On,
433 // which selects this particular move operation.
434 // Most likely, the compiler can pick other moves not
435 // listed here, and subsequently crash.
436 if (opc == TCE::MOVI1I32rr) return MOVE;
437
438 if (opc == TCE::INLINEASM) return INLINEASM;
439
440/* TODO: 64-bit support missing here? */
441
442 if (opc == TCE::ADDfri || opc == TCE::ADDhri) return "add";
443
444 if (opc == TCE::SUBfir || opc == TCE::SUBfri || opc == TCE::SUBhir ||
445 opc == TCE::SUBhri) return "sub";
446
447 if (opc == TCE::SUBfir) return "sub";
448 if (opc == TCE::SUBfri) return "sub";
449
450#ifdef TARGET64BIT
451 if (opc == TCE::ANDext) return "and64";
452 if (opc == TCE::XORbicmp) return "xor64";
453#else
454 if (opc == TCE::ANDext) return "and";
455 if (opc == TCE::XORbicmp) return "xor";
456#endif
457
458
459 if (opc == TCE::STQBrb) return "stq";
460 if (opc == TCE::STQBib) return "stq";
461 if (opc == TCE::STQBrj) return "stq";
462 if (opc == TCE::STQBij) return "stq";
463
464 if (opc == TCE::ST8Brb) return "st8";
465 if (opc == TCE::ST8Bib) return "st8";
466 if (opc == TCE::ST8Brj) return "st8";
467 if (opc == TCE::ST8Bij) return "st8";
468
469 // temporary RA register store/loads
470#ifdef TARGET64BIT
471 if (opc == TCE::ST64RAss) return "st64";
472 if (opc == TCE::LD64RAs) return "ld64";
473#else
474 if (opc == TCE::STWRArr) return "stw";
475 if (opc == TCE::LDWRAr) return "ldw";
476 if (opc == TCE::ST32RArr) return "st32";
477 if (opc == TCE::LD32RAr) return "ld32";
478#endif
479 if (opc == TCE::TCEBR) return "jump";
480 if (opc == TCE::TCEBRIND) return "jump";
481 if (opc == TCE::CALL) return "call";
482 if (opc == TCE::CALL_MEMrr) return "call";
483 if (opc == TCE::CALL_MEMri) return "call";
484
485 std::map<unsigned int, TCEString>::const_iterator opNameIt;
486
487 std::map<unsigned int, TCEString>::const_iterator i = opNames_.find(opc);
488 if (i == opNames_.end()) {
489 std::cerr << "ERROR: Couldn't find operation with opc: " << opc
490 << std::endl;
491 std::cerr << "Total ops: " << opNames_.size() << std::endl;
492/*
493 abort();
494*/
495 return "";
496 } else {
497 return i->second;
498 }
499}
500
501bool
502GeneratedTCEPlugin::validStackAccessOperation(const std::string& opName) const {
503 return validStackAccessOperations_.count(opName);
504}
505
506#include "TCEGenRegisterInfo.inc"
507
508/**
509 * Returns the specific register class representing registers belonging to
510 * a "computation node" inside a clustered-TTA.
511 *
512 * This can be used to limit the registers to be allocated from a single
513 * node, thus also suggest scheduling the operations there. For data
514 * parallel code.
515 *
516 * @param nodeId the ID of the node (starting from 0)
517 * @param current The "more general" register class to replace.
518 */
519const llvm::TargetRegisterClass*
521 unsigned nodeId, const llvm::TargetRegisterClass* current) const {
522
523 return NULL;
524}
525
526
527/**
528 * Returns the specific register class representing registers belonging to
529 * the "extras node" inside a clustered-TTA.
530 *
531 * @param current The "more general" register class to replace.
532 */
533const llvm::TargetRegisterClass*
535 const llvm::TargetRegisterClass* current) const {
536 const llvm::TargetRegisterInfo& TRI = *getRegisterInfo();
537
538 return NULL;
539}
540
541
542/**
543 * Maps llvm register numbers to target RF names.
544 */
545std::string
546GeneratedTCEPlugin::rfName(unsigned dwarfRegNum) {
547 if (regNames_.find(dwarfRegNum) == regNames_.end()) {
548 return "BYPASS_PSEUDO";
549 }
550 return regNames_[dwarfRegNum];
551}
552
553/**
554 * Maps llvm register numbers to target RF indices.
555 */
556unsigned
558 if (regIndices_.find(dwarfRegNum) == regIndices_.end()) {
559 return dwarfRegNum;
560 }
561 return regIndices_[dwarfRegNum];
562}
563
564
565std::string
569// Returns ID number of the return address register.
570unsigned
572 return TCE::RA;
573}
574
575extern "C" {
578
579 TCETargetMachinePlugin* instance =
580 new GeneratedTCEPlugin();
581 return instance;
582 }
584 TCETargetMachinePlugin* target) {
585 delete target;
586 }
587}
588
#define assert(condition)
#define NOP
#define MOVE(SRC, DST)
void LLVMInitializeTCETargetInfo()
void LLVMInitializeTCEStubTarget()
TCETargetMachinePlugin * create_tce_backend_plugin()
void delete_tce_backend_plugin(TCETargetMachinePlugin *target)
class TCEPluginInitializer myPlugin
static KeyType keyForValue(const MapType &aMap, const ValueType &aValue)
static bool containsValue(const MapType &aMap, const ValueType &aValue)
virtual bool analyzeCCBranch(llvm::MachineInstr &i, llvm::SmallVectorImpl< llvm::MachineOperand > &cond) const override
virtual int getIorOpcode(const EVT &vt) const override
virtual FunctionPass * createISelPass(TCETargetMachine *tm) override
std::map< unsigned, TCEString > opNames_
virtual std::tuple< int, int > getPointerAdjustment(int offset) const override
virtual bool has8bitLoads() const override
virtual bool hasUREM() const override
unsigned int extractElementLane(const llvm::MachineInstr &) const override
virtual std::vector< unsigned > getParamDRegNums() const override
virtual void registerTargetMachine(TCETargetMachine &tm) override
Plugin needs target machine for TragetLowering generation.
virtual std::vector< unsigned > getVectorRVDRegNums() const override
virtual int getMinOpcode(llvm::SDNode *n) const override
std::map< unsigned, unsigned > falsePredOps_
std::string dataASName() override
Returns name of the data address space.
virtual int getMinuOpcode(llvm::SDNode *n) const override
virtual std::string rfName(unsigned dwarfRegNum) override
virtual int getTruePredicateOpcode(unsigned opc) const override
virtual int getAddOpcode(const EVT &vt) const override
virtual bool hasSDIV() const override
virtual bool hasOperation(TCEString operationName) const override
Returns true in case the target supports the given osal operation.
unsigned int raPortDRegNum() override
Returns ID number of the return address register.
virtual bool canMaterializeConstant(const ConstantInt &ci) const override
virtual const TargetRegisterInfo * getRegisterInfo() const override
unsigned llvmRegisterId(const TCEString &ttaRegister) override
virtual bool hasROTL() const override
virtual int getMaxOpcode(llvm::SDNode *n) const override
virtual const TargetSubtargetInfo * getSubtarget() const override
virtual bool hasSXHW() const override
std::map< unsigned, unsigned > regIndices_
virtual int getLoadOpcode(const EVT &vt) const override
virtual int maxVectorSize() const override
virtual TargetTransformInfo getTargetTransformInfo(const Function &F) const override
virtual unsigned opcode(TCEString operationName) const override
Returns the opcode for the given osal operation, undefined if not found.
virtual TargetLowering * getTargetLowering() const override
virtual bool is64bit() const override
virtual bool hasSHL() const override
virtual int getStore(const TargetRegisterClass *rc) const override
virtual bool hasSREM() const override
std::map< unsigned, unsigned > truePredOps_
virtual bool hasSXQW() const override
virtual const TargetFrameLowering * getFrameLowering() const override
TCETools::CIStringSet validStackAccessOperations_
Set of valid LLVM opcodes for stack accesses.
virtual bool hasMUL() const override
virtual const llvm::TargetRegisterClass * nodeRegClass(unsigned nodeId, const llvm::TargetRegisterClass *current) const override
virtual int getLoad(const TargetRegisterClass *rc) const override
std::map< unsigned, TCEString > regNames_
virtual int getShlOpcode(const EVT &vt) const override
virtual const llvm::TargetRegisterClass * extrasRegClass(const llvm::TargetRegisterClass *current) const override
virtual bool isLittleEndian() const override
virtual bool hasSHRU() const override
virtual bool hasROTR() const override
virtual unsigned rvDRegNum() override
virtual MVT::SimpleValueType getDefaultType() const override
virtual bool hasSHR() const override
virtual bool hasUDIV() const override
virtual unsigned registerIndex(unsigned dwarfRegNum) override
virtual std::string operationName(unsigned opc) const override
virtual unsigned spDRegNum() override
Returns ID number of the stack pointer register.
virtual bool hasSQRTF() const override
virtual const TargetInstrInfo * getInstrInfo() const override
virtual int getFalsePredicateOpcode(unsigned opc) const override
virtual bool has16bitLoads() const override
virtual bool validStackAccessOperation(const std::string &opName) const override
Returns true if OSAL operation is valid for stack accesses.
std::map< TCEString, unsigned > ttallvmRegMap_
Map for TTA register to LLVM register id conversion.
virtual int getMaxuOpcode(llvm::SDNode *n) const override
virtual unsigned rvHighDRegNum() override
virtual unsigned fpDRegNum() override
Returns ID number of the frame pointer register.
virtual const TargetRegisterInfo & getRegisterInfo() const
TCEInstrInfo * instrInfo_
Target machine instruction info for the llvm framework.
unsigned stackAlignment() const
std::set< TCEString, CaseInsensitiveCmp > CIStringSet
FunctionPass * createTCEISelDag(TCETargetMachine &tm)