60 virtual const TargetInstrInfo*
getInstrInfo()
const override;
65 const Function& F)
const override;
66 virtual const TargetSubtargetInfo*
getSubtarget()
const override;
83 return TCE::KLUDGE_REGISTER;
97 virtual std::string
rfName(
unsigned dwarfRegNum)
override;
98 virtual unsigned registerIndex(
unsigned dwarfRegNum)
override;
104 return TCE::NoRegister;
109 virtual std::string
operationName(
unsigned opc)
const override;
111 const std::string& opName)
const override;
146 llvm::MachineInstr& i,
147 llvm::SmallVectorImpl<llvm::MachineOperand>& cond)
const override;
151 virtual int getLoad(
const TargetRegisterClass *rc)
const override;
152 virtual int getStore(
const TargetRegisterClass *rc)
const override;
160 const llvm::TargetRegisterClass* current)
const override;
163 const llvm::TargetRegisterClass* current)
const override;
182 int offset)
const override;
202#include "Backend.inc"
276const TargetInstrInfo*
284const TargetRegisterInfo*
292const TargetFrameLowering*
307 assert(
lowering_ != NULL &&
"TCETargetMachine has not registered to plugin.");
311const TargetSubtargetInfo*
331 if (mi.getDesc().getOpcode() == TCE::COPY) {
332 assert(mi.getNumOperands() >= 2);
333 const MachineOperand& src = mi.getOperand(1);
334 int subreg = src.getSubReg();
335 if (subreg > 0 && subreg < 9) {
343 std::map<unsigned int, unsigned int>::const_iterator i =
truePredOps_.find(opc);
352 std::map<unsigned int, unsigned int>::const_iterator i =
falsePredOps_.find(opc);
370 const std::string
MOVE =
"MOVE";
371 const std::string PSEUDO =
"PSEUDO";
372 const std::string
NOP =
"NOP";
373 const std::string INLINEASM =
"INLINEASM";
374 const std::string DEBUG_LABEL =
"DEBUG_LABEL";
375 const std::string DEBUG_VALUE =
"DEBUG_VALUE";
376 const std::string DEBUG_INSTR_REF =
"DEBUG_INSTR_REF";
377 const std::string DEBUG_VALUE_LIST =
"DEBUG_VALUE_LIST";
378 const std::string DEBUG_PHI =
"DEBUG_PHI";
380 if (opc == TCE::IMPLICIT_DEF)
return PSEUDO;
381 else if (opc == TCE::ADJCALLSTACKDOWN)
return PSEUDO;
382 else if (opc == TCE::ADJCALLSTACKUP)
return PSEUDO;
383 else if (opc == TCE::NOP)
return NOP;
384 if (opc == TCE::DBG_VALUE)
return DEBUG_VALUE;
385 if (opc == TCE::DBG_INSTR_REF)
return DEBUG_INSTR_REF;
386 if (opc == TCE::DBG_LABEL)
return DEBUG_LABEL;
387 if (opc == TCE::DBG_VALUE_LIST)
return DEBUG_VALUE_LIST;
388 if (opc == TCE::DBG_PHI)
return DEBUG_PHI;
390 if (opc == TCE::COPY)
return MOVE;
391 if (opc == TCE::MOVI1rr)
return MOVE;
392 if (opc == TCE::PRED_TRUE_MOVI1rr)
return "?MOVE";
393 if (opc == TCE::PRED_FALSE_MOVI1rr)
return "!MOVE";
394 if (opc == TCE::MOVI1ri)
return MOVE;
395 if (opc == TCE::PRED_TRUE_MOVI1ri)
return "?MOVE";
396 if (opc == TCE::PRED_FALSE_MOVI1ri)
return "!MOVE";
397 if (opc == TCE::MOVGri)
return MOVE;
398 if (opc == TCE::MOVI32rr)
return MOVE;
399 if (opc == TCE::PRED_TRUE_MOVI32rr)
return "?MOVE";
400 if (opc == TCE::PRED_FALSE_MOVI32rr)
return "!MOVE";
401 if (opc == TCE::MOVI32ri)
return MOVE;
402 if (opc == TCE::PRED_TRUE_MOVI32ri)
return "?MOVE";
403 if (opc == TCE::PRED_FALSE_MOVI32ri)
return "!MOVE";
404 if (opc == TCE::MOVI64sa)
return MOVE;
405 if (opc == TCE::PRED_TRUE_MOVI64sa)
return "?MOVE";
406 if (opc == TCE::PRED_FALSE_MOVI64sa)
return "!MOVE";
407 if (opc == TCE::MOV64ss)
return MOVE;
408 if (opc == TCE::PRED_TRUE_MOV64ss)
return "?MOVE";
409 if (opc == TCE::PRED_FALSE_MOV64ss)
return "!MOVE";
410 if (opc == TCE::MOVI64I1ss)
return MOVE;
413 if (opc == TCE::MOVff)
return MOVE;
414 if (opc == TCE::MOVfi)
return MOVE;
415 if (opc == TCE::MOVfk)
return MOVE;
416 if (opc == TCE::MOVI32I1rr)
return MOVE;
417 if (opc == TCE::MOVFI32rf)
return MOVE;
418 if (opc == TCE::MOVIF32fr)
return MOVE;
419 if (opc == TCE::MOVGrr)
return MOVE;
420 if (opc == TCE::MOVGI32rr)
return MOVE;
421 if (opc == TCE::MOVI32Grr)
return MOVE;
422 if (opc == TCE::MOVGI1rr)
return MOVE;
423 if (opc == TCE::MOVI1Grr)
return MOVE;
424 if (opc == TCE::MOVhh)
return MOVE;
425 if (opc == TCE::MOVhk)
return MOVE;
426 if (opc == TCE::MOVrh)
return MOVE;
427 if (opc == TCE::MOVhr)
return MOVE;
428 if (opc == TCE::MOVhi)
return MOVE;
429 if (opc == TCE::MOVsd)
return MOVE;
430 if (opc == TCE::MOVds)
return MOVE;
436 if (opc == TCE::MOVI1I32rr)
return MOVE;
438 if (opc == TCE::INLINEASM)
return INLINEASM;
442 if (opc == TCE::ADDfri || opc == TCE::ADDhri)
return "add";
444 if (opc == TCE::SUBfir || opc == TCE::SUBfri || opc == TCE::SUBhir ||
445 opc == TCE::SUBhri)
return "sub";
447 if (opc == TCE::SUBfir)
return "sub";
448 if (opc == TCE::SUBfri)
return "sub";
451 if (opc == TCE::ANDext)
return "and64";
452 if (opc == TCE::XORbicmp)
return "xor64";
454 if (opc == TCE::ANDext)
return "and";
455 if (opc == TCE::XORbicmp)
return "xor";
459 if (opc == TCE::STQBrb)
return "stq";
460 if (opc == TCE::STQBib)
return "stq";
461 if (opc == TCE::STQBrj)
return "stq";
462 if (opc == TCE::STQBij)
return "stq";
464 if (opc == TCE::ST8Brb)
return "st8";
465 if (opc == TCE::ST8Bib)
return "st8";
466 if (opc == TCE::ST8Brj)
return "st8";
467 if (opc == TCE::ST8Bij)
return "st8";
471 if (opc == TCE::ST64RAss)
return "st64";
472 if (opc == TCE::LD64RAs)
return "ld64";
474 if (opc == TCE::STWRArr)
return "stw";
475 if (opc == TCE::LDWRAr)
return "ldw";
476 if (opc == TCE::ST32RArr)
return "st32";
477 if (opc == TCE::LD32RAr)
return "ld32";
479 if (opc == TCE::TCEBR)
return "jump";
480 if (opc == TCE::TCEBRIND)
return "jump";
481 if (opc == TCE::CALL)
return "call";
482 if (opc == TCE::CALL_MEMrr)
return "call";
483 if (opc == TCE::CALL_MEMri)
return "call";
485 std::map<unsigned int, TCEString>::const_iterator opNameIt;
487 std::map<unsigned int, TCEString>::const_iterator i =
opNames_.find(opc);
489 std::cerr <<
"ERROR: Couldn't find operation with opc: " << opc
491 std::cerr <<
"Total ops: " <<
opNames_.size() << std::endl;
506#include "TCEGenRegisterInfo.inc"
519const llvm::TargetRegisterClass*
521 unsigned nodeId,
const llvm::TargetRegisterClass* current)
const {
533const llvm::TargetRegisterClass*
535 const llvm::TargetRegisterClass* current)
const {
548 return "BYPASS_PSEUDO";
#define assert(condition)
void LLVMInitializeTCETargetInfo()
void LLVMInitializeTCEStubTarget()
TCETargetMachinePlugin * create_tce_backend_plugin()
void delete_tce_backend_plugin(TCETargetMachinePlugin *target)
class TCEPluginInitializer myPlugin
virtual bool analyzeCCBranch(llvm::MachineInstr &i, llvm::SmallVectorImpl< llvm::MachineOperand > &cond) const override
virtual int getIorOpcode(const EVT &vt) const override
virtual FunctionPass * createISelPass(TCETargetMachine *tm) override
std::map< unsigned, TCEString > opNames_
virtual std::tuple< int, int > getPointerAdjustment(int offset) const override
virtual bool has8bitLoads() const override
virtual bool hasUREM() const override
unsigned int extractElementLane(const llvm::MachineInstr &) const override
virtual std::vector< unsigned > getParamDRegNums() const override
virtual void registerTargetMachine(TCETargetMachine &tm) override
Plugin needs target machine for TragetLowering generation.
virtual std::vector< unsigned > getVectorRVDRegNums() const override
virtual int getMinOpcode(llvm::SDNode *n) const override
std::map< unsigned, unsigned > falsePredOps_
std::string dataASName() override
Returns name of the data address space.
virtual int getMinuOpcode(llvm::SDNode *n) const override
virtual std::string rfName(unsigned dwarfRegNum) override
virtual int getTruePredicateOpcode(unsigned opc) const override
virtual int getAddOpcode(const EVT &vt) const override
virtual bool hasSDIV() const override
virtual bool hasOperation(TCEString operationName) const override
Returns true in case the target supports the given osal operation.
unsigned int raPortDRegNum() override
Returns ID number of the return address register.
virtual bool canMaterializeConstant(const ConstantInt &ci) const override
virtual const TargetRegisterInfo * getRegisterInfo() const override
unsigned llvmRegisterId(const TCEString &ttaRegister) override
virtual bool hasROTL() const override
virtual int getMaxOpcode(llvm::SDNode *n) const override
virtual const TargetSubtargetInfo * getSubtarget() const override
virtual bool hasSXHW() const override
std::map< unsigned, unsigned > regIndices_
virtual int getLoadOpcode(const EVT &vt) const override
virtual int maxVectorSize() const override
virtual TargetTransformInfo getTargetTransformInfo(const Function &F) const override
virtual unsigned opcode(TCEString operationName) const override
Returns the opcode for the given osal operation, undefined if not found.
virtual TargetLowering * getTargetLowering() const override
virtual bool is64bit() const override
virtual ~GeneratedTCEPlugin()
virtual bool hasSHL() const override
virtual int getStore(const TargetRegisterClass *rc) const override
virtual bool hasSREM() const override
std::map< unsigned, unsigned > truePredOps_
virtual bool hasSXQW() const override
virtual const TargetFrameLowering * getFrameLowering() const override
TCETools::CIStringSet validStackAccessOperations_
Set of valid LLVM opcodes for stack accesses.
virtual bool hasMUL() const override
virtual const llvm::TargetRegisterClass * nodeRegClass(unsigned nodeId, const llvm::TargetRegisterClass *current) const override
virtual int getLoad(const TargetRegisterClass *rc) const override
std::map< unsigned, TCEString > regNames_
virtual int getShlOpcode(const EVT &vt) const override
virtual const llvm::TargetRegisterClass * extrasRegClass(const llvm::TargetRegisterClass *current) const override
virtual void manualInitialize()
virtual bool isLittleEndian() const override
virtual bool hasSHRU() const override
virtual bool hasROTR() const override
virtual unsigned rvDRegNum() override
virtual MVT::SimpleValueType getDefaultType() const override
virtual bool hasSHR() const override
virtual bool hasUDIV() const override
virtual unsigned registerIndex(unsigned dwarfRegNum) override
virtual std::string operationName(unsigned opc) const override
virtual unsigned spDRegNum() override
Returns ID number of the stack pointer register.
virtual bool hasSQRTF() const override
virtual const TargetInstrInfo * getInstrInfo() const override
virtual int getFalsePredicateOpcode(unsigned opc) const override
virtual bool has16bitLoads() const override
virtual bool validStackAccessOperation(const std::string &opName) const override
Returns true if OSAL operation is valid for stack accesses.
std::map< TCEString, unsigned > ttallvmRegMap_
Map for TTA register to LLVM register id conversion.
virtual int getMaxuOpcode(llvm::SDNode *n) const override
virtual unsigned rvHighDRegNum() override
virtual unsigned fpDRegNum() override
Returns ID number of the frame pointer register.
virtual const TargetRegisterInfo & getRegisterInfo() const
TargetFrameLowering * frameInfo_
TCEInstrInfo * instrInfo_
Target machine instruction info for the llvm framework.
TCESubtarget * subTarget_
TargetLowering * lowering_
unsigned stackAlignment() const
FunctionPass * createTCEISelDag(TCETargetMachine &tm)