llvm::TCERegisterInfo Class Reference

#include <TCERegisterInfo.hh>

Inheritance diagram for llvm::TCERegisterInfo:

Collaboration diagram for llvm::TCERegisterInfo:

Public Member Functions
	TCERegisterInfo (const TargetInstrInfo &tii)
virtual	~TCERegisterInfo ()
void	eliminateCallFramePseudoInstr (MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
const MCPhysReg *	getCalleeSavedRegs (const MachineFunction *MF=0) const override
BitVector	getReservedRegs (const MachineFunction &MF) const override
bool	eliminateFrameIndex (MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=NULL) const override
unsigned	getRARegister () const
Register	getFrameRegister (const MachineFunction &mf) const override
bool	requiresRegisterScavenging (const MachineFunction &) const override
int	getDwarfRegNum (unsigned regNum, bool isEH) const
int	getLLVMRegNum (unsigned int, bool) const
bool	hasFP (const MachineFunction &MF) const
void	setTFI (const TCEFrameLowering *tfi)

Private Member Functions
void	setReservedVectorRegs (llvm::BitVector &reserved) const

Private Attributes
const TargetInstrInfo &	tii_
const TCEFrameLowering *	tfi_

Detailed Description

Class which handles registers in the TCE backend.

Definition at line 53 of file TCERegisterInfo.hh.

Constructor & Destructor Documentation

TCERegisterInfo()

TCERegisterInfo::TCERegisterInfo

(

const TargetInstrInfo &

tii

)

The Constructor.

Parameters

st	Subtarget architecture.
tii	Target architecture instruction info.

Definition at line 82 of file TCERegisterInfo.cc.

                                :
    TCEGenRegisterInfo(TCE::RA),
    tii_(tii) {
}

~TCERegisterInfo()

virtual llvm::TCERegisterInfo::~TCERegisterInfo ( )

inlinevirtual

Definition at line 56 of file TCERegisterInfo.hh.

{};

Member Function Documentation

eliminateCallFramePseudoInstr()

void llvm::TCERegisterInfo::eliminateCallFramePseudoInstr	(	MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I
	)		const

eliminateFrameIndex()

bool TCERegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  II, int  SPAdj, unsigned  FIOperandNum, RegScavenger *  RS = NULL  ) const

override

Definition at line 131 of file TCERegisterInfo.cc.

                            {
 
    MachineInstr &MI = *II;
    const TCETargetMachine& tm =
        dynamic_cast<const TCETargetMachine&>(
            MI.getParent()->getParent()->getTarget());
    // Attempt to catch stack accesses using unsupported operation.
    auto osalOpName = tm.operationName(MI.getOpcode());
    if (!tm.validStackAccessOperation(osalOpName)
        && osalOpName.find("MOVE") == std::string::npos) {
        THROW_EXCEPTION(CompileError,
            "Error: Stack address space is not reachable with operation '"
            + tm.operationName(MI.getOpcode()) + "'.\n"
            + "Forgot to add the operation to the stack LSU?");
    }
    static int lastBypassReg = 0;
    const TCEInstrInfo &TII = dynamic_cast<const TCEInstrInfo&>(tii_);
    assert(SPAdj == 0 && "Unexpected");
 
    DebugLoc dl = MI.getDebugLoc();
    int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
    // Addressable stack objects are accessed using neg. offsets from %fp
    // NO THEY ARE NOT! apwards from SP!
    MachineFunction &MF = *MI.getParent()->getParent();
 
    auto& frameinfo = MF.getFrameInfo();
 
    if (frameinfo.isSpillSlotObjectIndex(FrameIndex)) {
        for (MachineInstr::mmo_iterator i = MI.memoperands_begin();
             i != MI.memoperands_end(); i++) {
            const PseudoSourceValue* psv = (*i)->getPseudoValue();
            if (psv == NULL) {
                #ifdef LLVM_OLDER_THAN_15
                (*i)->setValue(new FixedStackPseudoSourceValue(FrameIndex, TII));
                #else
                (*i)->setValue(new FixedStackPseudoSourceValue(FrameIndex, tm));
                #endif
            }
        }
        if (MI.memoperands_begin() == MI.memoperands_end()) {
            // TODO: operation and size
            auto flags = static_cast<MachineMemOperand::Flags>(
                MI.mayLoad() * MachineMemOperand::MOLoad
                | MI.mayStore() * MachineMemOperand::MOStore);
            auto mmo = new MachineMemOperand(
                MachinePointerInfo(), flags, 0, Align(tfi_->stackAlignment()));
            #ifdef LLVM_OLDER_THAN_15
            mmo->setValue(new FixedStackPseudoSourceValue(FrameIndex, TII));
            #else
            mmo->setValue(new FixedStackPseudoSourceValue(FrameIndex, tm));
            #endif
            MI.addMemOperand(MF,  mmo);
        }
    }
 
    if (tfi_->hasFP(MF)) {
        int Offset = frameinfo.getObjectOffset(FrameIndex);
        int stackAlign = tfi_->stackAlignment();
        // FP storage space increases offset by stackAlign.
        Offset+= stackAlign;
        // RA storage space increases offset of incoming vars
        if (FrameIndex < 0  && frameinfo.hasCalls()
            && tfi_->containsCall(MF)) {
            Offset+= stackAlign;
        }
 
        if (Offset != 0) {
            // try to use a combined add+ld/st operation
            // (a base+offset load/store), if available
            // TODO: check that an offset port width is big enough for the
            // offset immediate.
 
 
            TCEString baseOffsetOp = "";
            TCEString originalOp = tm.operationName(MI.getOpcode());
 
            // TODO: are these the same for LE? ALD8 etc.?
            if (originalOp == "LDW" || originalOp == "LDHU" || 
                originalOp == "LDH" || originalOp == "LDQU" ||
                originalOp == "LDQ" || originalOp == "STW" ||
                originalOp == "STH" || originalOp == "STQ" ||
                originalOp == "LD32" || originalOp == "LDU16" || 
                originalOp == "LD16" || originalOp == "LDU8" ||
                originalOp == "LD8" || originalOp == "ST32" ||
                originalOp == "ST16" || originalOp == "ST8") {
                baseOffsetOp = TCEString("A") + originalOp;
            }
            if (baseOffsetOp != "" && tm.hasOperation(baseOffsetOp)) {
                const bool isStore = MI.getDesc().mayStore();
                unsigned storeDataReg = 0;
                uint64_t storeDataImm = 0;
 
                // the address should be always the 1st operand for the
                // base memory ops
                if (isStore) {
                    // operands: FI, 0, DATA
                    int storeDataOp = FIOperandNum + 2;
                    if (MI.getOperand(storeDataOp).isReg()) {                
                        storeDataReg = MI.getOperand(storeDataOp).getReg();
                    } else {
                        assert(MI.getOperand(storeDataOp).isImm());
                        storeDataImm = MI.getOperand(storeDataOp).getImm();
                    }
                }
 
                MI.setDesc(TII.get(tm.opcode(baseOffsetOp)));
                // now it should be safe to overwrite the 2nd operand
                // with the stack offset
                MI.getOperand(FIOperandNum).ChangeToRegister(TCE::FP, false);
                MI.getOperand(FIOperandNum + 1).setImm(Offset);
 
                if (isStore) {
                    // need to fix the 3rd input operand (the written data)
                    // for stores
                    if (storeDataReg) {
                        MI.getOperand(FIOperandNum + 2).ChangeToRegister(
                            storeDataReg, false);
                    } else {
                        MI.getOperand(FIOperandNum + 2).ChangeToImmediate(
                            storeDataImm);
                    }
                }
            } else { // FP, no base+offset ops
                MI.getOperand(FIOperandNum).ChangeToRegister(
                    TCE::KLUDGE_REGISTER, false, false, true/*iskill*/);
                //TODO clean up
                if (Offset > 0) {
                    BuildMI(
                        *MI.getParent(), II, MI.getDebugLoc(),
                        TII.get(ADDIMM), TCE::KLUDGE_REGISTER)
                            .addReg(TCE::FP).addImm(Offset);
                } else {
                    auto spOpcAndOffset = TII.getPointerAdjustment(Offset);
                    BuildMI(
                        *MI.getParent(), II, MI.getDebugLoc(),
                        TII.get(std::get<0>(spOpcAndOffset)),
                                TCE::KLUDGE_REGISTER)
                            .addReg(TCE::FP)
                            .addImm(std::get<1>(spOpcAndOffset));
                }
            }
        } else { // FP, offset 0
            MI.getOperand(FIOperandNum).ChangeToRegister(TCE::FP, false);
        }
    } else { // no FP
       int Offset = frameinfo.getObjectOffset(FrameIndex) + 
            frameinfo.getStackSize();
 
       if (Offset == 0) {
            MI.getOperand(FIOperandNum).ChangeToRegister(TCE::SP, false);
            #ifdef LLVM_OLDER_THAN_16
            return;
            #else
            return false;
            #endif
        }
 
       // try to use a combined add+ld/st operation (a base+offset load/store), 
       // if available
       // TODO: check that an offset port width is big enough for the offset 
       // immediate
       const TCETargetMachine& tm = 
           dynamic_cast<const TCETargetMachine&>(
               MI.getParent()->getParent()->getTarget());
 
 
       TCEString baseOffsetOp = "";
       TCEString originalOp = tm.operationName(MI.getOpcode());
 
       // TODO: are these the same for LE? ALD8 etc.?
       if (originalOp == "LDW" || originalOp == "LDHU" || 
           originalOp == "LDH" || originalOp == "LDQU" ||
           originalOp == "LDQ" || originalOp == "STW" ||
           originalOp == "STH" || originalOp == "STQ" ||
           originalOp == "LD32" || originalOp == "LDU16" || 
           originalOp == "LD16" || originalOp == "LDU8" ||
           originalOp == "LD8" || originalOp == "ST32" ||
           originalOp == "ST16" || originalOp == "ST8") {
           baseOffsetOp = TCEString("A") + originalOp;
       }
       if (baseOffsetOp != "" && tm.hasOperation(baseOffsetOp)) {
           const bool isStore = MI.getDesc().mayStore();
           unsigned storeDataReg = 0;
           uint64_t storeDataImm = 0;
 
           // the address should be always the 1st operand for the
           // base memory ops
           if (isStore) {
               // operands: FI, 0, DATA
               int storeDataOp = FIOperandNum + 2;
               if (MI.getOperand(storeDataOp).isReg()) {                
                   storeDataReg = MI.getOperand(storeDataOp).getReg();
               } else {
                   assert(MI.getOperand(storeDataOp).isImm());
                   storeDataImm = MI.getOperand(storeDataOp).getImm();
               }
           }
 
           MI.setDesc(TII.get(tm.opcode(baseOffsetOp)));
           // now it should be safe to overwrite the 2nd operand
           // with the stack offset
           MI.getOperand(FIOperandNum).ChangeToRegister(TCE::SP, false);
           MI.getOperand(FIOperandNum + 1).setImm(Offset);
 
           if (isStore) {
               // need to fix the 3rd input operand (the written data)
               // for stores
               if (storeDataReg) {
                   MI.getOperand(FIOperandNum + 2).ChangeToRegister(
                       storeDataReg, false);
               } else {
                   MI.getOperand(FIOperandNum + 2).ChangeToImmediate(
                       storeDataImm);
               }
           }
       } else {
           // generate the sp + offset addition before the use
           unsigned int tmp = 0;
 
           LLVMTCECmdLineOptions* options =
               dynamic_cast<LLVMTCECmdLineOptions*>(
                   Application::cmdLineOptions());
           if (RS != NULL) {
               tmp = RS->FindUnusedReg(&INTEGER_REG_CLASS);
           }
 
           if (tmp != 0) {
               MI.getOperand(FIOperandNum).ChangeToRegister(
                   tmp, false, false, true);
               BuildMI(
                   *MI.getParent(), II, MI.getDebugLoc(), TII.get(ADDIMM),
                   tmp).addReg(TCE::SP).addImm(Offset);
           } else {
               MI.getOperand(FIOperandNum).ChangeToRegister(
                   TCE::KLUDGE_REGISTER, false);
               BuildMI(
                   *MI.getParent(), II, MI.getDebugLoc(), TII.get(ADDIMM),
                   TCE::KLUDGE_REGISTER).addReg(TCE::SP).addImm(Offset);
           }
       }
    }
    #ifdef LLVM_OLDER_THAN_16
    return;
    #else
    return false;
    #endif
}

References ADDIMM, assert, Application::cmdLineOptions(), llvm::TCEInstrInfo::getPointerAdjustment(), llvm::TCETargetMachine::hasOperation(), INTEGER_REG_CLASS, llvm::TCETargetMachine::opcode(), llvm::TCETargetMachine::operationName(), options, THROW_EXCEPTION, and llvm::TCETargetMachine::validStackAccessOperation().

Here is the call graph for this function:

getCalleeSavedRegs()

const MCPhysReg * TCERegisterInfo::getCalleeSavedRegs ( const MachineFunction *  MF = 0 ) const

override

Returns list of callee saved registers.

Definition at line 92 of file TCERegisterInfo.cc.

                                                                   {
    static const uint16_t calleeSavedRegs[] = { TCE::FP, 0 };
    if (hasFP(*MF)) {
        return calleeSavedRegs+1; // skip first, it's reserved
    } else {
        return calleeSavedRegs;
    }
}

References hasFP().

Here is the call graph for this function:

getDwarfRegNum()

int llvm::TCERegisterInfo::getDwarfRegNum	(	unsigned	regNum,
		bool	isEH
	)		const

getFrameRegister()

Register TCERegisterInfo::getFrameRegister ( const MachineFunction &  mf ) const

override

Definition at line 416 of file TCERegisterInfo.cc.

                                                                 {
    if (hasFP(mf)) {
        return TCE::FP;
    } else {
        return 0;
    }
}

References hasFP().

Here is the call graph for this function:

getLLVMRegNum()

int llvm::TCERegisterInfo::getLLVMRegNum	(	unsigned int	,
		bool
	)		const

getRARegister()

unsigned TCERegisterInfo::getRARegister

(

)

const

Re-issue the specified 'original' instruction at the specific location targeting a new destination register.

Parameters

mbb	Machine basic block of the new instruction.
i	Position of the new instruction in the basic block.
destReg	New destination register.
orig	Original instruction.

void TCERegisterInfo::reMaterialize( MachineBasicBlock& mbb, MachineBasicBlock::iterator i, unsigned destReg, const MachineInstr* orig) const { assert(false && "It really was used"); MachineInstr* mi = mbb.getParent()->CloneMachineInstr(orig); mi->getOperand(0).setReg(destReg); mbb.insert(i, mi); } Not implemented: When is this method even called?

Definition at line 410 of file TCERegisterInfo.cc.

                                     {
    assert(false && "Remove this assert if this is really called.");
    return TCE::RA;
}

References assert.

getReservedRegs()

BitVector TCERegisterInfo::getReservedRegs ( const MachineFunction &  mf ) const

override

Returns list of reserved registers.

Definition at line 105 of file TCERegisterInfo.cc.

                                                                {
 
    LLVMTCECmdLineOptions* options =
        dynamic_cast<LLVMTCECmdLineOptions*>(Application::cmdLineOptions());
 
    assert(&mf != NULL);
    BitVector reserved(getNumRegs());
    reserved.set(TCE::SP);
    reserved.set(TCE::KLUDGE_REGISTER);
    reserved.set(TCE::RA);
    const MachineFrameInfo* mfi = &mf.getFrameInfo();
    if (mfi->hasCalls() && tfi_->containsCall(mf)) {
        for (int i = 0; i < argRegCount; i++) {
            reserved.set(ArgRegs[i]);
        }
        setReservedVectorRegs(reserved);
    }
    if (hasFP(mf)) {
        reserved.set(TCE::FP);
    }
 
    return reserved;
}

References assert, Application::cmdLineOptions(), llvm::TCEFrameLowering::containsCall(), hasFP(), options, setReservedVectorRegs(), and tfi_.

Here is the call graph for this function:

hasFP()

bool TCERegisterInfo::hasFP

(

const MachineFunction &

MF

)

const

Definition at line 425 of file TCERegisterInfo.cc.

                                                      {
    return tfi_->hasFP(MF);
}

References llvm::TCEFrameLowering::hasFP(), and tfi_.

Referenced by getCalleeSavedRegs(), getFrameRegister(), and getReservedRegs().

Here is the call graph for this function:

requiresRegisterScavenging()

bool TCERegisterInfo::requiresRegisterScavenging ( const MachineFunction &  ) const

override

Definition at line 430 of file TCERegisterInfo.cc.

                                                                        {
    return false;
}

setReservedVectorRegs()

void llvm::TCERegisterInfo::setReservedVectorRegs ( llvm::BitVector &  reserved ) const

private

Referenced by getReservedRegs().

setTFI()

void llvm::TCERegisterInfo::setTFI ( const TCEFrameLowering *  tfi )

inline

Definition at line 84 of file TCERegisterInfo.hh.

{ tfi_ = tfi; };

References tfi_.

Referenced by llvm::TCEFrameLowering::TCEFrameLowering().

Member Data Documentation

tfi_

const TCEFrameLowering* llvm::TCERegisterInfo::tfi_

private

Definition at line 89 of file TCERegisterInfo.hh.

Referenced by getReservedRegs(), hasFP(), and setTFI().

tii_

const TargetInstrInfo& llvm::TCERegisterInfo::tii_

private

Definition at line 88 of file TCERegisterInfo.hh.

---

The documentation for this class was generated from the following files:

• TCERegisterInfo.hh
• TCERegisterInfo.cc