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63 delete port_it->second;
64 port_it->second = NULL;
67 PortGroupPrototypeContainer::iterator portGroup_it =
70 delete portGroup_it->second;
71 portGroup_it->second = NULL;
121 "imem_data",
"IMEMWIDTHINMAUS*IMEMMAUWIDTH",
BIT_VECTOR,
174 "Attempted to initialize twice.");
202 return clkPortPrototype.
clone(direction !=
IN);
210 static const InBitPort rstxPortPrototype(
212 return rstxPortPrototype.
clone(direction !=
IN);
@ FETCHBLOCK
Signal is TTA instruction block block containing (compressed) instruction.
TTAMachine::Machine * machine
the architecture definition of the estimated processor
@ BIT_VECTOR
Several bits.
static NetlistPort * resetPort(Direction direction=IN)
NetlistPort * createPort(SignalType type, Direction direction=IN) const
Convenience class for output bit ports.
Direction direction() const
void registerPortGroups()
@ UNDEFINED
Signal does not have specified usage.
static void initializeContext(const TTAMachine::Machine &machine, const IDF::MachineImplementation &impl)
@ INSTRUCTION_LINE
Signal group type for serial TTA instruction bus.
#define assert(condition)
static const TTAMachine::Machine * staticMachine_
The creation context for singleton instance.
@ STALL
Signal to stopping destination device.
Convenience class for input ports.
PortPrototypeContainer portPrototypes_
The creation context.
static PortFactory * instance()
static const IDF::MachineImplementation * staticImplementation_
The creation context for singleton instance.
void registerPortGroup(SignalGroupType type, const NetlistPortGroup *portGroup)
@ ADDRESS
Signal holds address.
virtual NetlistPort * clone(bool asMirrored=false) const
SignalGroup assignedSignalGroup() const
static NetlistPort * clockPort(Direction direction=IN)
@ READ_REQUEST
Signal to make read request.
static PortFactory * instance_
Singleton instance of the factory.
NetlistPortGroup * createPortGroup(SignalGroupType type) const
static NetlistPort * create(SignalType type, Direction direction=IN)
PortGroupPrototypeContainer portGroupPrototypes_
Registered NetlistPortGroup prototypes.
Signal assignedSignal() const
SignalGroupType type() const
Direction
Direction of the port.
Convenience class for input bit ports.
Convenience class for output ports.
void registerPort(SignalType, const NetlistPort *port)