ProGe::NetlistPort Class Reference

#include <NetlistPort.hh>

Inheritance diagram for ProGe::NetlistPort:

Collaboration diagram for ProGe::NetlistPort:

Public Member Functions
	NetlistPort (const std::string &name, const std::string &widthFormula, int realWidth, DataType dataType, Direction direction, BaseNetlistBlock &parent, Signal signal=Signal())
	NetlistPort (const std::string &name, int realWidth, DataType dataType, Direction direction, BaseNetlistBlock &parent, Signal signal=Signal())
	NetlistPort (const std::string &name, const std::string &widthFormula, DataType dataType, Direction direction, BaseNetlistBlock &parent, Signal signal=Signal())
	NetlistPort (const std::string &name, const std::string &widthFormula, DataType dataType, Direction direction, Signal signal=Signal())
virtual	~NetlistPort ()
bool	resolveRealWidth (int &width) const
NetlistPort *	copyTo (BaseNetlistBlock &newParent, std::string newName="") const
virtual NetlistPort *	clone (bool asMirrored=false) const
std::string	name () const
void	rename (const std::string &newname)
std::string	widthFormula () const
void	setWidthFormula (const std::string &newFormula)
bool	realWidthAvailable () const
int	realWidth () const
DataType	dataType () const
Direction	direction () const
void	setDirection (Direction direction)
bool	hasParentBlock () const
const BaseNetlistBlock &	parentBlock () const
BaseNetlistBlock &	parentBlock ()
void	setToStatic (StaticSignal value) const
void	unsetStatic () const
bool	hasStaticValue () const
StaticSignal	staticValue () const
void	assignSignal (Signal signal)
Signal	assignedSignal () const

Private Member Functions
void	setParent (BaseNetlistBlock *parent)
	NetlistPort (const NetlistPort &other, bool asMirrored=false)

Private Attributes
std::string	name_
	Name of the port. More...
std::string	widthFormula_
	Formula for the width of the port. More...
int	realWidth_
	Real width of the port. More...
DataType	dataType_
	Data type of the port. More...
Direction	direction_
	Direction of the port. More...
BaseNetlistBlock *	parentBlock_
	The parent netlist block. More...
bool	hasStaticValue_
	Indicates if port is connected to vcc or gnd. More...
StaticSignal	staticValue_
	Static signal value. More...
Signal	signal_
	Assigned port usage. More...

Friends
class	BaseNetlistBlock

Detailed Description

Represents a port in the netlist. Ports are the vertices of the graph that represents the netlist. From the ports, it is possible to reach the parent netlist blocks.

Definition at line 70 of file NetlistPort.hh.

Constructor & Destructor Documentation

NetlistPort() [1/5]

ProGe::NetlistPort::NetlistPort	(	const std::string &	name,
		const std::string &	widthFormula,
		int	realWidth,
		DataType	dataType,
		Direction	direction,
		BaseNetlistBlock &	parent,
		Signal	signal = Signal()
	)

Constructor. Creates a netlist port with a defined bit width.

Creates a port that has a known bit width. Adds the port automatically to the parent block. If a formula for calculating the bit width is given, it should match the actual bit width (an integer number). No check is performed, however, to make sure that the formula is compatible with the actual width. In case of mismatch, the error can be detected only after generation (for example, in a logic synthesis tool).

Parameters

name	Name of the port.
widthFormula	Formula for calculating the width.
realWidth	Actual width of the port.
dataType	Type of the data.
direction	Direction of the port.
parent	The parent netlist block.

Exceptions

OutOfRange

If the actual width is not positive ( <0 ).

Definition at line 64 of file NetlistPort.cc.

    : name_(name),
      widthFormula_(widthFormula),
      realWidth_(realWidth),
      dataType_(dataType),
      direction_(direction),
      parentBlock_(&parent),
      hasStaticValue_(false),
      staticValue_(StaticSignal::GND),
      signal_(signal) {
 
    // TODO: there might still be possible regressions from changing realWidth
    // check to "< 0" from "< 1" 
    // RF (and IU?) opcode ports may have width 0
    if (realWidth_ < 0 ) {
        TCEString msg = "Port ";
        msg << name << " has a negative width.";
        throw OutOfRange(__FILE__, __LINE__, __func__, msg);
    }
 
    parent.addPort(this);
}

References __func__, ProGe::BaseNetlistBlock::addPort(), name(), and realWidth_.

Referenced by clone(), and copyTo().

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NetlistPort() [2/5]

ProGe::NetlistPort::NetlistPort	(	const std::string &	name,
		int	realWidth,
		DataType	dataType,
		Direction	direction,
		BaseNetlistBlock &	parent,
		Signal	signal = Signal()
	)

Constructor. Creates a netlist port with a defined bit width, and derive formula from the integer value

Parameters

name	Name of the port.
realWidth	Actual width of the port.
dataType	Type of the data.
direction	Direction of the port.
parent	The parent netlist block.

Exceptions

OutOfRange

If the actual width is not positive ( <0 ).

Definition at line 105 of file NetlistPort.cc.

    : name_(name),
      widthFormula_(Conversion::toString(realWidth)),
      realWidth_(realWidth),
      dataType_(dataType),
      direction_(direction),
      parentBlock_(&parent),
      hasStaticValue_(false),
      staticValue_(StaticSignal::GND),
      signal_(signal) {
 
    // TODO: there might still be possible regressions from changing realWidth
    // check to "< 0" from "< 1" 
    // RF (and IU?) opcode ports may have width 0
    if (realWidth_ < 0 ) {
        TCEString msg = "Port ";
        msg << name << " has a negative width.";
        throw OutOfRange(__FILE__, __LINE__, __func__, msg);
    }
 
    parent.addPort(this);
}

References __func__, ProGe::BaseNetlistBlock::addPort(), name(), and realWidth_.

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NetlistPort() [3/5]

ProGe::NetlistPort::NetlistPort	(	const std::string &	name,
		const std::string &	widthFormula,
		DataType	dataType,
		Direction	direction,
		BaseNetlistBlock &	parent,
		Signal	signal = Signal()
	)

Constructor. Creates a new netlist port.

Creates a port that has its bit width defined symbolically, by an expression (formula). Adds the port automatically to the parent block.

Parameters

name	Name of the port.
widthFormula	Formula for calculating the width.
dataType	Type of the data.
direction	Direction of the port.
parent	The parent netlist block.

Definition at line 146 of file NetlistPort.cc.

    : name_(name),
      widthFormula_(widthFormula),
      realWidth_(-1),
      dataType_(dataType),
      direction_(direction),
      parentBlock_(&parent),
      hasStaticValue_(false),
      staticValue_(StaticSignal::GND),
      signal_(signal) {
 
    parent.addPort(this);
}

References ProGe::BaseNetlistBlock::addPort().

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NetlistPort() [4/5]

ProGe::NetlistPort::NetlistPort	(	const std::string &	name,
		const std::string &	widthFormula,
		DataType	dataType,
		Direction	direction,
		Signal	signal = Signal()
	)

Definition at line 186 of file NetlistPort.cc.

    : name_(name),
      widthFormula_(widthFormula),
      realWidth_(-1),
      dataType_(dataType),
      direction_(direction),
      parentBlock_(nullptr),
      hasStaticValue_(false),
      staticValue_(StaticSignal::GND),
      signal_(signal) {
}

~NetlistPort()

ProGe::NetlistPort::~NetlistPort ( )

virtual

Destructor.

Removes itself from the parent netlist block.

Definition at line 270 of file NetlistPort.cc.

                          {
    if (hasParentBlock()) {
        parentBlock_->removePort(this);
    }
}

References hasParentBlock(), parentBlock_, and ProGe::BaseNetlistBlock::removePort().

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NetlistPort() [5/5]

ProGe::NetlistPort::NetlistPort ( const NetlistPort &  other, bool  asMirrored = false  )

private

Copy constructor. Copies everything except parent block reference since one NetlistBlock may not have ports with identical names.

Definition at line 170 of file NetlistPort.cc.

    : name_(other.name_),
      widthFormula_(other.widthFormula_),
      realWidth_(other.realWidth_),
      dataType_(other.dataType_),
      direction_(other.direction_),
      parentBlock_(nullptr),
      hasStaticValue_(other.hasStaticValue_),
      staticValue_(other.staticValue_),
      signal_(other.signal_) {
 
    if (asMirrored) {
        direction_ = NetlistTools::mirror(other.direction_);
    }
}

References direction_, and ProGe::NetlistTools::mirror().

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Member Function Documentation

assignedSignal()

Signal ProGe::NetlistPort::assignedSignal

(

)

const

Return signal assigned to the port.

Definition at line 455 of file NetlistPort.cc.

                                  {
    return signal_;
}

References signal_.

Referenced by ProGe::NetlistPortGroup::clone(), clone(), ProGe::Netlist::connect(), copyTo(), ProGe::NetlistPortGroup::hasPortBySignal(), ProGe::BaseNetlistBlock::hasPortsBy(), ProGe::NetlistPortGroup::portBySignal(), ProGe::BaseNetlistBlock::portsBy(), and ProGe::PortFactory::registerPort().

assignSignal()

void ProGe::NetlistPort::assignSignal

(

Signal

signal

)

Assign signal to signify usage of the port.

Definition at line 447 of file NetlistPort.cc.

                                       {
    signal_ = signal;
}

References signal_.

clone()

NetlistPort * ProGe::NetlistPort::clone ( bool  asMirrored = false ) const

virtual

Definition at line 258 of file NetlistPort.cc.

                                        {
    NetlistPort* newPort = new NetlistPort(*this, asMirrored);
    assert(newPort->assignedSignal().type() == this->assignedSignal().type());
    return newPort;
}

References assert, assignedSignal(), NetlistPort(), and ProGe::Signal::type().

Referenced by ProGe::PortFactory::clockPort(), ProGe::ProcessorWrapperBlock::handleUnconnectedPorts(), ProGe::NetlistPortGroup::NetlistPortGroup(), and ProGe::PortFactory::resetPort().

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copyTo()

NetlistPort * ProGe::NetlistPort::copyTo	(	BaseNetlistBlock &	newParent,
		std::string	newName = ""
	)		const

DEPRECATED

Definition at line 231 of file NetlistPort.cc.

                             {
    if (newName == "")
        newName = this->name();
 
    if (realWidthAvailable()) {
        return new NetlistPort(
            newName, widthFormula(), realWidth(), dataType(), direction(), 
            newParent, assignedSignal());
    } else {
        int width = 0;
        if (resolveRealWidth(width)) {
            return new NetlistPort(
                newName, widthFormula(), width, dataType(), direction(), 
                newParent, assignedSignal());
        } else {
            return new NetlistPort(
                newName, widthFormula(), dataType(), direction(), newParent,
                assignedSignal());
        }
    }
    return NULL; 
}

References assignedSignal(), dataType(), direction(), name(), NetlistPort(), realWidth(), realWidthAvailable(), resolveRealWidth(), and widthFormula().

Referenced by ProGe::NetlistBlock::shallowCopy(), and ProGe::BaseNetlistBlock::shallowCopy().

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dataType()

DataType ProGe::NetlistPort::dataType

(

)

const

Returns the data type of the port.

Returns

The data type of the port.

Definition at line 362 of file NetlistPort.cc.

                            {
    return dataType_;
}

References dataType_.

Referenced by ProGe::Netlist::connect(), MemoryGenerator::connectPorts(), PlatformIntegrator::connectToplevelPort(), copyTo(), ProGe::VHDLNetlistWriter::portSignalName(), ProGe::VHDLNetlistWriter::portSignalType(), ProGe::VerilogNetlistWriter::portSignalType(), ProGe::NetlistVisualization::portWidthToString(), ProGe::VHDLNetlistWriter::signalAssignment(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VHDLNetlistWriter::writeConnection(), ProGe::VerilogNetlistWriter::writePortDeclaration(), ProGe::VHDLNetlistWriter::writePortDeclaration(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VerilogNetlistWriter::writeSignalAssignments(), and ProGe::VHDLNetlistWriter::writeSignalAssignments().

direction()

Direction ProGe::NetlistPort::direction

(

)

const

Returns the direction of the port.

Returns

The direction of the port.

Definition at line 373 of file NetlistPort.cc.

                             {
    return direction_;
}

References direction_.

Referenced by AvalonMMMasterInterface::addPort(), DefaultDecoderGenerator::completeDecoderBlock(), ProGe::BaseNetlistBlock::connectClocks(), ProGe::BaseNetlistBlock::connectResets(), PlatformIntegrator::connectToplevelPort(), copyTo(), SOPCBuilderFileGenerator::countAvalonMMMasters(), ProGe::PortFactory::createPort(), SOPCBuilderFileGenerator::exportSignal(), AvalonMMMasterInterface::isValidPort(), ProGe::NetlistGenerator::mapNetlistPort(), ProGe::NetlistTools::mirror(), ProGe::NetlistVisualization::printPort(), setDirection(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VHDLNetlistWriter::writeConnection(), ProGe::VHDLNetlistWriter::writePortDeclaration(), ProGe::VerilogNetlistWriter::writePortDeclaration(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writeSignalAssignments(), and ProGe::VerilogNetlistWriter::writeSignalAssignments().

hasParentBlock()

bool ProGe::NetlistPort::hasParentBlock

(

)

const

Returns true if ports is attached to some netlist block. Otherwise, returns false.

Definition at line 390 of file NetlistPort.cc.

                                  {
    return parentBlock_ != NULL;
}

References parentBlock_.

Referenced by ProGe::BaseNetlistBlock::addPort(), rename(), and ~NetlistPort().

hasStaticValue()

bool ProGe::NetlistPort::hasStaticValue

(

)

const

Definition at line 423 of file NetlistPort.cc.

                                  {
    return hasStaticValue_;
}

References hasStaticValue_.

Referenced by ProGe::ProcessorWrapperBlock::handleUnconnectedPorts(), ProGe::VHDLNetlistWriter::portSignalName(), ProGe::VerilogNetlistWriter::portSignalName(), ProGe::VHDLNetlistWriter::writeSignalDeclarations(), and ProGe::VerilogNetlistWriter::writeSignalDeclarations().

name()

std::string ProGe::NetlistPort::name

(

)

const

Returns the name of the port.

Returns

The name of the port.

Definition at line 283 of file NetlistPort.cc.

                        {
    return name_;
}

References name_.

Referenced by ProGe::GeneratableFUNetlistBlock::addInOperand(), AvalonMMMasterInterface::addIrqInterface(), ProGe::GeneratableFUNetlistBlock::addOutOperand(), AvalonMMMasterInterface::addPort(), ProGe::BaseNetlistBlock::addPort(), ProGe::NetlistTools::addPrefixToPortName(), AlteraHibiDpRamGenerator::connectPorts(), PlatformIntegrator::connectToplevelPort(), copyTo(), MemoryGenerator::corePortName(), SOPCBuilderFileGenerator::countAvalonMMMasters(), SOPCBuilderFileGenerator::createInterfaces(), SOPCBuilderFileGenerator::exportSignal(), ProGe::NetlistGenerator::fuGuardPort(), SOPCBuilderFileGenerator::handleAvalonSignal(), AlmaIFIntegrator::integrateCore(), AvalonMMMasterInterface::isValidPort(), ProGe::NetlistVisualization::listConnections(), ProGe::NetlistVisualization::listNetlistDescriptors(), ProGe::NetlistGenerator::loadPort(), IPXactClkInterface::mapPortsToInterface(), IPXactResetInterface::mapPortsToInterface(), IPXactHibiInterface::mapPortsToInterface(), Stratix3DevKitIntegrator::mapToplevelPorts(), Stratix2DSPBoardIntegrator::mapToplevelPorts(), NetlistPort(), ProGe::VHDLNetlistWriter::portSignalName(), ProGe::VerilogNetlistWriter::portSignalName(), ProGe::NetlistVisualization::printPort(), realWidth(), rename(), ProGe::NetlistGenerator::rfOpcodePort(), ProGe::NetlistBlock::shallowCopy(), ProGe::BaseNetlistBlock::shallowCopy(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VHDLNetlistWriter::writeConnection(), ProGe::VHDLNetlistWriter::writePortDeclaration(), ProGe::VerilogNetlistWriter::writePortDeclaration(), ProGe::VerilogNetlistWriter::writePortMappings(), and ProGe::VHDLNetlistWriter::writePortMappings().

parentBlock() [1/2]

BaseNetlistBlock& ProGe::NetlistPort::parentBlock

(

)

parentBlock() [2/2]

BaseNetlistBlock & ProGe::NetlistPort::parentBlock

(

)

const

Returns the parent netlist block.

Returns

The parent netlist block.

Definition at line 400 of file NetlistPort.cc.

                               {
    return *parentBlock_;
}

References parentBlock_.

Referenced by ProGe::BaseNetlistBlock::addPort(), ProGe::NetlistGenerator::fuGuardPort(), ProGe::NetlistVisualization::listConnections(), ProGe::NetlistVisualization::listNetlistDescriptors(), ProGe::NetlistGenerator::loadPort(), ProGe::VHDLNetlistWriter::parameterWidthValue(), ProGe::VHDLNetlistWriter::portSignalName(), ProGe::VerilogNetlistWriter::portSignalName(), ProGe::BaseNetlistBlock::removePort(), resolveRealWidth(), ProGe::NetlistGenerator::rfOpcodePort(), ProGe::VHDLNetlistWriter::usesParameterWidth(), ProGe::VHDLNetlistWriter::writeConnection(), ProGe::VerilogNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writePortMappings(), ProGe::VHDLNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalAssignments(), ProGe::VerilogNetlistWriter::writeSignalDeclarations(), and ProGe::VHDLNetlistWriter::writeSignalDeclarations().

realWidth()

int ProGe::NetlistPort::realWidth

(

)

const

Returns the actual bit width of the port.

Returns

The actual bit width.

Exceptions

NotAvailable

If the actual width is not known.

Definition at line 348 of file NetlistPort.cc.

                             {
    if (!realWidthAvailable()) {
        throw NotAvailable(__FILE__, __LINE__, __func__, "Port " + name()
                           + " doesn't have actual bit width.");
    }
    return realWidth_;
}

References __func__, name(), realWidth_, and realWidthAvailable().

Referenced by AvalonMMMasterInterface::addIrqInterface(), XilinxBlockRamGenerator::addMemory(), AvalonMMMasterInterface::addPort(), PlatformIntegrator::connectToplevelPort(), copyTo(), SOPCBuilderFileGenerator::exportSignal(), HDLPort::HDLPort(), DefaultDecoderGenerator::opcodeWidth(), ProGe::VerilogNetlistWriter::portSignalName(), ProGe::VHDLNetlistWriter::portSignalType(), ProGe::VerilogNetlistWriter::portSignalType(), ProGe::NetlistVisualization::portWidthToString(), ProGe::VHDLNetlistWriter::writeSignalDeclarations(), and ProGe::VerilogNetlistWriter::writeSignalDeclarations().

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realWidthAvailable()

bool ProGe::NetlistPort::realWidthAvailable

(

)

const

Tells whether the actual bit width of the port is known.

Returns

True if the width is known, otherwise false.

Definition at line 334 of file NetlistPort.cc.

                                      {
    // TODO: there might still be possible regressions from changing realWidth
    // check to allow zero.
    return realWidth_ >= 0;
}

References realWidth_.

Referenced by AvalonMMMasterInterface::addIrqInterface(), AvalonMMMasterInterface::addPort(), PlatformIntegrator::connectToplevelPort(), copyTo(), SOPCBuilderFileGenerator::exportSignal(), HDLPort::HDLPort(), ProGe::VHDLNetlistWriter::portSignalType(), ProGe::VerilogNetlistWriter::portSignalType(), ProGe::NetlistVisualization::portWidthToString(), realWidth(), ProGe::VHDLNetlistWriter::writeSignalDeclarations(), and ProGe::VerilogNetlistWriter::writeSignalDeclarations().

rename()

void ProGe::NetlistPort::rename

(

const std::string &

newname

)

Sets new name of the port.

Returns

The name of the port.

Definition at line 294 of file NetlistPort.cc.

                                            {
    if (hasParentBlock()) {
        if(parentBlock_->port(newname, false) == nullptr ||
            parentBlock_->port(newname, false) == this) {
            name_ = newname;
        } else {
            THROW_EXCEPTION(ObjectAlreadyExists, "Port to be renamed ("
                + name() +") to " + newname +
                " is not unique within the block.");
        }
    } else {
        name_ = newname;
    }
}

References hasParentBlock(), name(), name_, parentBlock_, ProGe::BaseNetlistBlock::port(), and THROW_EXCEPTION.

Referenced by ProGe::NetlistTools::addPrefixToPortName(), and ProGe::LoopBufferBlock::LoopBufferBlock().

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resolveRealWidth()

bool ProGe::NetlistPort::resolveRealWidth

(

int &

width

)

const

Definition at line 204 of file NetlistPort.cc.

                                              {
    
    std::string formula = widthFormula();
    // check if it is a parameter
    for (size_t i = 0; i < parentBlock().netlist().parameterCount(); i++) {
        Parameter param = parentBlock().netlist().parameter(i);
        if (param.name() == formula) {
            width = Conversion::toInt(param.value());
            return true;
        }
    }
    
    // check if formula is a plain number
    bool success = false;
    try {
        width = Conversion::toInt(formula);
        success = true;
    } catch (Exception& e) {
        success = false;
    }
    return success;
}

References ProGe::Parameter::name(), ProGe::BaseNetlistBlock::netlist(), ProGe::Netlist::parameter(), ProGe::Netlist::parameterCount(), parentBlock(), Conversion::toInt(), ProGe::Parameter::value(), and widthFormula().

Referenced by copyTo().

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setDirection()

void ProGe::NetlistPort::setDirection

(

Direction

direction

)

Sets direction of the port.

Definition at line 381 of file NetlistPort.cc.

                                             {
    direction_ = direction;
}

References direction(), and direction_.

Referenced by ProGe::NetlistTools::mirror().

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setParent()

void ProGe::NetlistPort::setParent ( BaseNetlistBlock *  parent )

private

Set parent block of this port.

Parameters

newParent

The new parent. Can be NULL too.

Definition at line 439 of file NetlistPort.cc.

                                               {
    parentBlock_ = parent;
}

References parentBlock_.

Referenced by ProGe::BaseNetlistBlock::addPort(), and ProGe::BaseNetlistBlock::removePort().

setToStatic()

void ProGe::NetlistPort::setToStatic

(

StaticSignal

value

)

const

Definition at line 410 of file NetlistPort.cc.

                                                 {
 
    hasStaticValue_ = true;
    staticValue_ = value;
}

References hasStaticValue_, and staticValue_.

Referenced by DefaultICDecoderGenerator::addDummyIfetchDebugPorts(), and HDLPort::convertToNetlistPort().

setWidthFormula()

void ProGe::NetlistPort::setWidthFormula

(

const std::string &

newFormula

)

Changes port's width formula.

Definition at line 324 of file NetlistPort.cc.

                                                        {
    widthFormula_ = newFormula;
}

References widthFormula_.

Referenced by DefaultICDecoderGenerator::addRV32MicroCode().

staticValue()

StaticSignal ProGe::NetlistPort::staticValue

(

)

const

Definition at line 429 of file NetlistPort.cc.

                               {
    return staticValue_;
}

References staticValue_.

Referenced by ProGe::VHDLNetlistWriter::portSignalName(), and ProGe::VerilogNetlistWriter::portSignalName().

unsetStatic()

void ProGe::NetlistPort::unsetStatic

(

)

const

Definition at line 417 of file NetlistPort.cc.

                               {
 
    hasStaticValue_ = false;
}

References hasStaticValue_.

Referenced by DefaultICDecoderGenerator::generateDebuggerCode().

widthFormula()

std::string ProGe::NetlistPort::widthFormula

(

)

const

Returns the formula that defines the width of the port.

Returns

The formula.

Definition at line 316 of file NetlistPort.cc.

                                {
    return widthFormula_;
}

References widthFormula_.

Referenced by ProGe::ProcessorWrapperBlock::addDataMemory(), ProGe::ProcessorWrapperBlock::addDataMemory2(), DefaultDecoderGenerator::completeDecoderBlock(), PlatformIntegrator::connectToplevelPort(), copyTo(), DefaultICDecoderGenerator::generateDebuggerCode(), ProGe::VHDLNetlistWriter::parameterWidthValue(), ProGe::VHDLNetlistWriter::portSignalType(), ProGe::VerilogNetlistWriter::portSignalType(), ProGe::NetlistVisualization::portWidthToString(), resolveRealWidth(), ProGe::VHDLNetlistWriter::usesParameterWidth(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writePortDeclaration(), ProGe::VHDLNetlistWriter::writePortDeclaration(), and ProGe::VHDLNetlistWriter::writePortMappings().

Friends And Related Function Documentation

BaseNetlistBlock

friend class BaseNetlistBlock

friend

Definition at line 72 of file NetlistPort.hh.

Member Data Documentation

dataType_

DataType ProGe::NetlistPort::dataType_

private

Data type of the port.

Definition at line 144 of file NetlistPort.hh.

Referenced by dataType().

direction_

Direction ProGe::NetlistPort::direction_

private

Direction of the port.

Definition at line 146 of file NetlistPort.hh.

Referenced by direction(), NetlistPort(), and setDirection().

hasStaticValue_

bool ProGe::NetlistPort::hasStaticValue_

mutableprivate

Indicates if port is connected to vcc or gnd.

Definition at line 150 of file NetlistPort.hh.

Referenced by hasStaticValue(), setToStatic(), and unsetStatic().

name_

std::string ProGe::NetlistPort::name_

private

Name of the port.

Definition at line 138 of file NetlistPort.hh.

Referenced by name(), and rename().

parentBlock_

BaseNetlistBlock* ProGe::NetlistPort::parentBlock_

private

The parent netlist block.

Definition at line 148 of file NetlistPort.hh.

Referenced by hasParentBlock(), parentBlock(), rename(), setParent(), and ~NetlistPort().

realWidth_

int ProGe::NetlistPort::realWidth_

private

Real width of the port.

Definition at line 142 of file NetlistPort.hh.

Referenced by NetlistPort(), realWidth(), and realWidthAvailable().

signal_

Signal ProGe::NetlistPort::signal_

private

Assigned port usage.

Definition at line 154 of file NetlistPort.hh.

Referenced by assignedSignal(), and assignSignal().

staticValue_

StaticSignal ProGe::NetlistPort::staticValue_

mutableprivate

Static signal value.

Definition at line 152 of file NetlistPort.hh.

Referenced by setToStatic(), and staticValue().

widthFormula_

std::string ProGe::NetlistPort::widthFormula_

private

Formula for the width of the port.

Definition at line 140 of file NetlistPort.hh.

Referenced by setWidthFormula(), and widthFormula().

---

The documentation for this class was generated from the following files:

• NetlistPort.hh
• NetlistPort.cc